How to verify well layer connectivity with soft checks

By Terry Meeks In the landscape of modern IC chip verification, ensuring the connectivity from diffusion layers to well regions…

AI/ML rules at the 2024 SPIE Advanced Lithography + Patterning symposium

The SPIE Advanced Lithography + Pattering symposiums were held from 25-29 February this year with enthusiastic and sizable attendance. The…

Unlocking the future with a digital twin for semiconductor manufacturing

By Srividya Jayaram In semiconductor manufacturing, staying ahead means embracing smarter processes. The rise in demand and the need to…

Using a shift left strategy to address block/chip design challenges during design-stage verification

By David Abercrombie For IC designers, striking the right balance between tight deadlines and limited resources is a constant challenge….

How to get accurate inductance extraction for superconductor ICs

By Hossam Sarhan and Dusan Petranovic Supporting the high performance and reliability needed for artificial intelligence (AI), data centers and…

The secret to Calibre software quality – AnaCov, our in-house code coverage analysis tool

By Mustafa Naeem, Ahmed Tahoon, Omar Ragi, and Reem El-Adawi In the realm of software testing, accurately tracking and analyzing…

Unraveling the 3DIC shift left strategy: Navigating the world of multi-dimensional ICs

By John Ferguson IC design’s evolution continues to push the boundaries of Moore’s law to new heights. One of the…

Mastering parasitic extraction at the 3 nm process node

By Dilan Heredia and Karen Chow Designing integrated circuits (ICs) for the 3 nm process node poses challenges never seen…

Why PID issues matter to IC chip designers, and how to combat them

By Derong Yan Integrated circuit (IC) chip designers are constantly striving to meet ever-increasing standards of reliability and performance in…