VLSI optimization—a bridge too far?

source: Andrew Shiva/CC BY-SA 4.0By Sherif Hany – Mentor, A Siemens Business

Job without end. How about job done?

Have you ever seen any of the world’s massive steel bridges, like the Forth bridge near Edinburgh, or the Golden Gate bridge in San Francisco? If so, you’ve probably heard the colloquial story that keeping them painted to protect against the elements is a never-ending task. Except, in 2011, a new coating was used on the Forth bridge that will last for 25 years. Job done.

Optimizing and revalidating your VLSI design can also feel like a never-ending task. Re-running validation flows, generating metadata…maybe it’s job security of a sort, but a tedious, time-consuming sort of work. Necessary, but not much to look forward to every day.

What about using a “new coating” that, okay, it won’t last 25 years, but it will shorten up that optimization cycle considerably, improving both your productivity and turnaround time? The Calibre® PERC™ reliability platform leverages an innovative approach that allows designers to generate design metadata one time during the initial verification flow. Then, when checks are re-run, the process can skip the data generation for those steps in which the data is untouched. Depending on which flow you’re running, this data reuse can improve your runtimes anywhere from 2-8X while maintaining the accuracy of the results. This smart one-time metadata generation can not only be used in verification flows, such as voltage-aware design rule checking or point to point and current density verification, but also in DFM applications, design profiling, and failure analysis. Job done!

If you’re tired of “painting” your VLSI design over and over and over, the details are explained in our Semiconductor Digest article, VLSI Design Optimization and Validation (pg 26). Give it a read, and if you have questions, put down your paintbrush and contact us for more information.

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