Verification Horizons - Siemens Software

Siemens at DVCon U.S. 2026

February 22, 2026

DVCon U.S. returns to a larger venue at the Hyatt Regency Santa Clara. The expanded rooms and exhibit hall are intended to support a program heavily focused on AI in verification. Siemens EDA will have a significant presence throughout the week. This includes a sponsored luncheon panel, a major conference keynote, technical papers, and multiple tutorials that advance the state of verification, agentic AI, CDC and RDC standardization, and HLS to FPGA cloud prototyping.

By Dennis Brophy

4 MIN READ

An illustration of a chip next to a computer screen representing an engineer doing formal verification

Beyond simulation: Unlocking absolute certainty in hardware design with formal verification

February 16, 2026

Explore how formal verification is revolutionizing hardware design by offering not just confidence, but absolute certainty in design’s correctness.

By Nicolae Tusinschi

3 MIN READ

Ai network plexus technology background 3D illustration

System Verifier

January 5, 2026

System Verifier enables digitally engineered, model-based systems verification, reducing integration failures by unifying multilayer Model-based systems engineering (MBSE) modeling and threaded verification.

By Julie Weber

2 MIN READ

FutureCast 2026: A Special Holiday Edition of BUGGED OUT

December 9, 2025

As another year closes, the semiconductor industry finds itself in a moment of transition—one where the pace of innovation is…

By Harry Foster

2 MIN READ

Introducing BUGGED OUT — A new bite-sized podcast for verification engineers

November 10, 2025

BUGGED OUT Podcast

By Harry Foster

2 MIN READ

New RTL Modeling Constructs in Verilog

October 16, 2025

I’ve been packing up my office as Siemens is closing my location. This marks the longest I’ve ever spent in a single office, a whopping 15 years. Coincidentally, I was in the same building earlier with another company, Avant! for an additional 2 years. I’ve got a box of stuff from previous jobs that I rarely unpack. But it happened to go through it and found the proceedings from what was to become the first DVCon in 1992. I doubt these proceedings exist anywhere in digital form.

In the proceedings was a paper I published about a new RTL modeling construct I added to Verilog before it became an IEEE standard. It eventually became known as a NonBlocking Assignment (NBA).

By Dave Rich

9 MIN READ

Interchange format standard in hierarchical CDC and RDC analysis

October 6, 2025

For large designs with numerous asynchronous clocks and resets, there is a growing need to do clock domain crossing (CDC) and reset domain crossing (RDC) analysis in a hierarchical way. This allows parallelization of sub-block and noiseless analysis and helps reduce SoC runtime and speed closure of CDC and RDC issues at the SoC level. Conversely, it poses challenges for design houses using third-party IP in ensuring the compatibility of their hierarchical data models (HDM) in the case of multiple EDA tools usage.

By Farhad Ahmed

2 MIN READ

From manageability to 3.0: Unlocking the future with UCIe verification

September 26, 2025

The semiconductor industry is steadily moving toward multi-die integration, where chiplets from different sources are combined within a single package (known as a system in package or SiP) to deliver higher performance, scalability, and efficiency. The Universal Chiplet Interconnect Express (UCIe) standard is the backbone of this movement, offering a high-bandwidth, low-latency interconnect that enables heterogeneous chiplets to operate as one system.

UCIe 3.0 raises the bar once again. By adding higher data rates, runtime recalibration, priority sideband messaging, low-power sideband operation, and circular buffer transport, the standard improves both performance and efficiency. But it also increases verification complexity.

By Ujjwal Negi and Prashant Dixit

5 MIN READ