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First day of school 2021 - 2022

Learn Formal the Easy Way

The sight of kids going back to school can prompt feelings of joy and renewal…

Performance Profiling How-To (Make My Testbench Faster)

Here’s the situation… You’re DV lead. You and your team are at month 10 of…

Simulation Performance Profiling Like a Pro

New product development is the fun part of working with Siemens. And over the past…

Parking lot with an Automobile and Pickup, plus class variables

Class Variables and $cast

Introduction My previous post showed how SystemVerilog class variables can refer to base and derived…

SPICE Turns 50!

50 years ago on 4 August 1971, the IEEE Journal of Solid-State Circuits published the…

Deploying Formal in a DO-254 Program

The primary focus of DO-254, referred to as ED-80 in Europe, is hardware reliability of…

Base and derived classes and their handles

Class Variables and Assignments in SystemVerilog

Introduction Good OOP style says you should start your project with a common base class…

Qrun-ing Optimized Build Flows in Questasim

Qrun-ing with Questasim For Questasim users, qrun will be a welcome surprise. Admittedly, I’ve never…

Runtime checks with the $cast() method

Introduction Verilog was always known for its lack of type checking, treating everything as just…