Latest Posts

DAC 2022: The Digital Twin Reimagined – One Model To Rule Them All?

To many of us in the EDA world, using the term “digital twin” to describe how customers’ electronically model their…

DAC 2022: Siemens EDA Experts Share Practical Cloud Solutions

Customers have been running Siemens EDA’s tools and flows in the cloud since 2005; and today at any given time…

Learn How to Verify PCIe Integrity and Data Encryption (IDE) Security Logic at the 2022 PCI SIG Developer Conference

Making sure that digital logic enables secure data to safely flow through a system is a critical task for RTL…

Siemens EDA at Verification Futures 2022

Siemens EDA is excited to participate at Verification Futures 2022 as a Gold Sponsor. This year’s conference is a hybrid…

Pro Tip: Planning to Land Your Spacecraft on Mars? You Will Need CDC, RDC, and Formal Property Checking

If you are an engineer at one of the growing number of entities looking to land a spacecraft on Mars…

Verilog & VHDL Debug & Weeding

A short exploration through using better debugging tools for better productivity.

Siemens EDA at the 59th Design Automation Conference

Mark your calendars for the upcoming 59th Design Automation Conference, and welcome back to the beautiful city by the bay—San…

Engineering Tools

Clearing the Fog of ISO 26262 Tool Qualification

Developing products to the ISO 26262 standard requires many activities across multiple disciplines. One of those activities is ensuring the…

RISC-V

Do You Know for Sure Your RISC-V RTL Doesn’t Contain Any Surprises?

Given the relative novelty and complexity of RISC-V RTL designs, whether you are buying a commercially supported core or downloading…