Verification Horizons - Siemens Software

Discover a smarter approach to In-System Test verification at ITC 2026

October 6, 2026

In-System Test is rapidly becoming a critical capability for advanced silicon, enabling new approaches to manufacturing test, silicon health monitoring,…

By Jake Wiltgen

2 MIN READ

UALink over UCIe 3.0: Maximizing Performance for Chiplet-based Designs

October 1, 2026

This blog is about how UALink and UCIe 3.0 come together to make chiplet‑based accelerator systems scale efficiently. It explains,…

By Mundru Sriram Bhaskar Teja

5 MIN READ

The next chapter for PCIe: Chiplet integration with UCIe

September 25, 2026

From processors and accelerators to storage, networking, and memory subsystems, PCI Express (PCIe) has been the backbone of modern compute…

By Kartik Sahajpal and Prashant Dixit

4 MIN READ

Smarter FMEDA, Safer Designs: The Questa One Verification IQ Compliance Advisor Story

September 18, 2026

FMEDA Challenges in Modern Semiconductor and Automotive Projects Ever wondered why creating an FMEDA, a fundamental requirement for functional safety…

By Yaswanth-Kumar Kalla

4 MIN READ

Why verification traceability must evolve for modern systems

September 11, 2026

Learn how Questa One VeriThreader delivers comprehensive verification traceability from systems to silicon

By Jake Wiltgen

4 MIN READ

2026 Siemens EDA and Wilson Research Group Functional Verification Study

The 2026 Functional Verification Study: Evidence of a New Verification Operating State

September 8, 2026

Explore key findings from the 2026 Siemens EDA and Wilson Research Group Functional Verification Study, including the latest trends, challenges, and priorities shaping functional verification.

By Harry Foster

3 MIN READ

Join Moses Satyasekaran at DVCon Taiwan on September 8 to explore how agentic AI could reshape design, verification, and the role of the engineer

Why Agentic AI Could Redefine the Future of Design and Verification

August 31, 2026

Discover how agentic AI is reshaping design and verification—and why the rise of the Design & Verification Scientist matters. Join Moses Satyasekaran at DVCon Taiwan on September 8 for a keynote exploring what comes next.

By Harry Foster

2 MIN READ