2026 Siemens EDA & Wilson Research Group Functional Verification Study

Are We Looking Beyond the Numbers in the 2026 Functional Verification Study?

The 2026 Functional Verification Study reveals troubling trends in first-silicon success and project schedules. But the bigger story may be how the nature of verification complexity is changing. Join Harry Foster as he explores what the findings mean for building confidence in today’s increasingly interconnected SoCs.

DVCon India 2025 - 10th Anniversary

Siemens at DVCon India 2025: Driving the Future of Design and Verification

DVCon India 2025, taking place on September 10–11 at the Radisson Blu, Marathahalli, Bengaluru, will mark a special milestone—its 10th anniversary. Over the past decade, DVCon India has grown into one of the region’s most influential conferences for design and verification professionals. Siemens will be prominently featured across vision talks, technical papers, posters, and workshops, showcasing its leadership in AI-driven EDA, hardware-assisted verification, and formal methodologies.

Exploring essential concepts in Formal Verification

What is a witness? is it the same as a counterexample? A witness is a sequence of inputs that demonstrates…

Assertions and benefits of abstractions in Formal Verification

How are assertions specified? Assertions are typically specified using languages like SystemVerilog Assertions (SVA) or Property Specification Language (PSL). These…

Understanding Formal Verification

What is formal verification? Formal verification is a method to ensure that a hardware design behaves as intended by using…

Accellera Day at DVCon U.S. 2024

DVCon U.S. 2024 will be a week packed with paper sessions, tutorials, panels, keynotes and more on the latest in…

Pro Tip: Planning to Land Your Spacecraft on Mars? You Will Need CDC, RDC, and Formal Property Checking

If you are an engineer at one of the growing number of entities looking to land a spacecraft on Mars…

How to Reduce the Complexity of Formal Analysis – Part 5 – Memory Abstraction

How to Reduce the Complexity of Formal Analysis – Part 5 – Memory Abstraction

When big counters and memories are in the active logic cone of an assertion that keeps coming up as “inconclusive”,…

How to Reduce the Complexity of Formal Analysis – Part 4 – Counter Abstraction

How to Reduce the Complexity of Formal Analysis – Part 4 – Counter Abstraction

When big counters and memories are in the active logic cone of an assertion that keeps coming up as “inconclusive”,…