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SystemVerilog: Implicit handles

Introduction In the last blog post [SC(SECL1] Farmer Ted asked you to keep track of his animals and you wrote some…

DVCon India 2022 – In-Person Again!

Accellera plays host to the global Design & Verification Conferences.  For the past few years, the DVCons have been virtual…

SystemVerilog: Class Member Visibility

SystemVerilog: Class Member Visibility

Introduction Farmer Ted wants to keep track of the animals on his property and asks you to write the code….

Connect test module with interface to design with individual ports

SystemVerilog: What is a Virtual Interface?

When I learned the SystemVerilog verification features, one concept had me baffled – virtual interfaces. What are these and why…

Siemens EDA VIP at Flash Memory Summit

Come and see what Siemens EDA’s Verification IP experts are talking about at the Flash Memory Summit event. This annual…

Finding Data

Finding Data Another weekend of weeding. Dark Star – Ceanothus – A California Lilac in the picture. (Not a weed)….

Advisors

Safety Lifecycle Evaluation Part 2: The Data is Compelling

Introduction This post builds upon the first post titled Key findings of a safety critical lifecycle evaluation. Simply put, productivity…

DAC Skytalk: Joe Sawicki on “Delivering ‘Smarter’ Faster – The Future of EDA & AI”

It’s hard to believe that the Design Automation Conference (DAC) is coming up in less than two weeks. As always,…

How to Mitigate the Impact of Security and Safety Flaws on Automotive ICs

Nearly 7 years ago security researchers uncovered how to remotely access and control the steering, cruise control, and braking system…