I’m Excited About Formal Property Checking! My Journey From Skeptic to Believer

Yup. You read that right. I’m excited about formal property checking. To put it mildly,…

SystemVerilog Race Condition Challenge Responses

As promised, here is my response to Mentor’s SystemVerilog Race Condition Challenge Race #1 Blocking…

The Correlation Between Safety Tool Chains and Nuclear Disarmament

The title may have you wondering how the heck I’m going to tie together two…

Great Upcoming Web Events on the Horizon

We’ve got some great online web seminars coming up in the next few weeks. Please…

DAC 2020 Paper Report: Easy Deadlock Verification and Debug with Advanced Formal Verification

At this year’s Design Automation Conference (DAC), Formal verification was everywhere – in posters, papers,…

SystemVerilog

Time for Another Revision of the SystemVerilog IEEE 1800 Standard

Between Accellera and the IEEE, there have been seven revisions of the SystemVerilog Language Reference…

SystemVerilog Race Condition Challenge

If there’s one thing I’ve learned since coming to Mentor early last year, it’s that…

Accellera at Virtual DAC 2020

Functional Safety: Accellera’s Virtual Lunch Event Focus With DAC 2020 going virtual, the opportunities for…

Verification Horizons DAC 2020 Issue Now Available

Whether you’re attending the Virtual DAC this week or not, I am happy to share…