Verification Academy 2026 webinar round-up
It’s hard to believe, but we’re already almost halfway through 2026! Time flies when you’re innovating, and here at Siemens, we’ve been busy bringing you a fantastic lineup of webinars to keep you at the forefront of technology.
We’ve covered a lot of ground in the first half of the year, diving deep into everything from advanced verification techniques to the exciting world of AI/ML design. Whether you’re looking to streamline your verification process, tackle complex design challenges, or future-proof your designs, our experts have shared invaluable insights and practical guidance.
Let’s take a quick look back at some of the incredible webinars we’ve hosted so far in 2026. If you missed any of these, you can catch up on demand!
January 2026
Constrained randomization and functional coverage in Questa One Sim with UVVM
Dive into the powerful world of Questa One Sim with UVVM in this session, where you’ll discover how its new constrained randomization features can revolutionize your verification process. Learn to dynamically generate UVVM-compliant stimuli, even for the most complex design constraints, ensuring thorough exploration of your verification scenarios. This webinar is your gateway to more efficient and effective verification strategies.
Formal verification made simple: a practical guide for FPGA designers
Unravel the complexities of formal verification with this practical guide designed specifically for FPGA designers. Discover how SFV seamlessly integrates into your current design flow, providing an automatic and exhaustive method to catch elusive bugs that traditional simulation might miss. This session will empower you to enhance the reliability of your control logic, interfaces, and complex state machines with ease.
Simulating CDC reconvergence: validating robustness with Questa One Sim’s metastability injection
Explore Questa One Sim’s innovative metastability injection capability, bringing critical non-deterministic delay validation directly into your simulation environment. This webinar demonstrates how to actively model and inject varying metastability delays into synchronizer paths, allowing for rigorous verification of sequential reconvergence logic. Discover how to validate the robustness of your designs against metastability with this groundbreaking feature.
Supercharge your CDC & RDC analysis with the power of AI/ML
Tackle the complexities of CDC/RDC verification head-on by leveraging the power of AI/ML with CDC/RDC Assist. This webinar reveals how machine learning automates and accelerates causality analysis, significantly streamlining the identification and resolution of violations. Learn to supercharge your verification process, making it faster and more efficient than ever before.
Cut weeks from debug: rapid first – level bug hunting with Inspect and Check X
Transform your verification process with Inspect and Check X, intuitive ‘push-button’ tools designed for rapid first-level bug hunting. This webinar offers a practical deep dive into their core functionalities, showcasing an efficient workflow from setup to insightful results analysis. Discover how these powerful solutions empower you to quickly identify and resolve design bugs, leading to a more robust design and accelerated time-to-market.
February 2026
Close coverage faster with Questa One Sim’s unreachability analysis
Tackle the persistent ‘Last Mile problem’ in functional verification with Questa One Sim’s automated unreachability analysis. This webinar delves into why traditional coverage closure methods often fall short, especially as projects near completion. Discover a transformative solution that helps you efficiently close coverage gaps faster, ensuring your ASIC and FPGA design projects meet their ambitious goals.
Don’t miss CDC bugs in low power designs: formal meets power aware CDC
Ensure the integrity of your low-power designs by tackling elusive CDC bugs with Questa CDC Power Aware analysis. This webinar demonstrates how Questa CDC combines exhaustive formal analysis with automated protocol assertions to prove safe crossings and effectively filter functionally false positives. Discover how to confidently verify your low-power designs against critical CDC issues.
Future-proof your designs: the power of Verify Property in digital verification
Future-proof your designs with the power of Verify Property in digital verification. This webinar unveils cutting-edge tools that empower engineers to identify complex structural issues, connectivity errors, and X-propagation problems early in the design cycle, all without the need for stimulus generation. Discover how to streamline your verification workflow, accelerate time-to-market, and deliver robust, high-quality designs while significantly reducing costly re-spins and debug cycles.
Securing next-generation interconnects: PCIe® Gen7 security verification
Dive into the critical world of PCIe® Gen7 security verification. This session highlights the latest advancements in PCIe Gen7 security and demonstrates how Avery Verification IP, built on deep expertise, enables early validation of TDISP and IDE functionality. Discover how to achieve comprehensive protocol and security coverage, faster compliance, and ultimately reduce risk and time-to-market for your secure PCIe designs.
AI assisted FPU verification using Questa One SFV
Explore the cutting-edge of AI-assisted FPU verification with Questa One SFV. This webinar delves into the critical role of Floating-Point Hardware design in the AI revolution, addressing the need for both fast computing with low precision and very high precision in calculations. Discover how Questa One’s AI-assisted tools for Static Formal can help generate full formal verification checkers for user-defined functionality, including complex floating-point operations.
Unlock efficiency: next-gen verification with Questa Check Register & Questa Check Connect
Unlock next-gen verification efficiency with Questa Check Register and Questa Check Connect. This webinar will guide you through the automated verification of memory-mapped registers and connections in SoC designs. Discover how these powerful tools eliminate manual errors, accelerate verification processes, and ensure your registers and SoC connections are flawless and reliable. It’s perfect for teams looking to significantly reduce time-to-market and elevate design quality.
March 2026
Shift-left Compute Subsystem RTL sign-off with Software Aware VIP
Accelerate your Compute Subsystem RTL sign-off with a powerful shift-left methodology. This webinar introduces a scalable approach for developing and verifying designs like Arm® Neoverse™ V3 Compute Subsystem (CSS)-based systems. Discover how to leverage Avery Protocol VIP, CSS VIP, Software Aware VIP, Arm Fast Models, and QEMU models to achieve faster simulation and sign-off, ultimately speeding up your development and verification cycles.
April 2026
From apps to orchestration: Agentic AI for autonomous RTL signoff with Questa One Agentic Toolkit
Step into the future of RTL signoff with Agentic AI and the Questa One Agentic Toolkit. This webinar unveils how this revolutionary toolkit, built on the industry-leading Questa One verification solution, transforms verification from isolated applications into intelligently orchestrated workflows. Discover how purpose-built Agentic AI autonomously reasons, plans, and executes strategies, all while keeping engineers in control with approval at critical decision points, paving the way for autonomous RTL sign-off.
May 2026
Generating quality properties for formal verification of a design
Boost your formal verification productivity by leveraging AI to generate high-quality properties. This webinar demonstrates how Questa One SFV provides critical prompts for AI agents and LLMs, enabling them to produce usable properties for your designs. Discover the seamless integration with VS Code, allowing for property generation, checking, and interactive debugging all within a familiar and efficient development environment.
Breaking bandwidth barriers in the AI era: scaling PCIe with Retimers and optical innovation
Break through bandwidth barriers in the AI era by scaling PCIe with retimers and optical innovation. This webinar will delve into PCIe Gen8 Retimer and Optical retimer technologies, highlighting their key applications, especially in GPU and AI accelerators. You’ll also gain a clear understanding of the Four-Retimer Aware (FRA) feature and the essential rules governing loopback, lane margining, and SKP ordered sets, ensuring robust and high-speed data transfer.
Looking forward
We hope you’ve found these webinars helpful and insightful. Stay tuned for more exciting content in the second half of 2026! We’re always working to bring you the latest and greatest in technology and innovation.
