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SystemVerilog: Implicit handles

Introduction In the last blog post [SC(SECL1] Farmer Ted asked you to keep track of his animals and you wrote some…

SystemVerilog: Class Member Visibility

SystemVerilog: Class Member Visibility

Introduction Farmer Ted wants to keep track of the animals on his property and asks you to write the code….

Siemens EDA VIP at Flash Memory Summit

Come and see what Siemens EDA’s Verification IP experts are talking about at the Flash Memory Summit event. This annual…

How to Mitigate the Impact of Security and Safety Flaws on Automotive ICs

Nearly 7 years ago security researchers uncovered how to remotely access and control the steering, cruise control, and braking system…

DAC 2022: The Digital Twin Reimagined – One Model To Rule Them All?

To many of us in the EDA world, using the term “digital twin” to describe how customers’ electronically model their…

Learn How to Verify PCIe Integrity and Data Encryption (IDE) Security Logic at the 2022 PCI SIG Developer Conference

Making sure that digital logic enables secure data to safely flow through a system is a critical task for RTL…

Pro Tip: Planning to Land Your Spacecraft on Mars? You Will Need CDC, RDC, and Formal Property Checking

If you are an engineer at one of the growing number of entities looking to land a spacecraft on Mars…

Growing Complexity of Automotive ASICs

I was recently asked to compile some data from our 2020 Wilson Research Group Functional Verification Study focused specifically on…

Webinar Preview: Practical Flows for Continuous Integration

But First, The Backstory… I’ll take you back to May 4th 2020 to the last in a series of verification…