Prologue: The 2020 Wilson Research Group Functional Verification Study

This is the first in a sequence of blogs that presents the findings from our…

SystemVerilog Race Condition Challenge Responses

As promised, here is my response to Mentor’s SystemVerilog Race Condition Challenge Race #1 Blocking…

SystemVerilog

Time for Another Revision of the SystemVerilog IEEE 1800 Standard

Between Accellera and the IEEE, there have been seven revisions of the SystemVerilog Language Reference…

SystemVerilog Race Condition Challenge

If there’s one thing I’ve learned since coming to Mentor early last year, it’s that…

DAC 2020: A Rare Virtual Opportunity in Professional Development!

Probably one of the most important pieces of advice I ever received was given to…

PCIe Gen5: A pathway to address Data Explosion and Emerging Technologies

As the technology scales or shrinks, there are always some bottlenecks that need to be…

Asking better questions on the Verification Academy Forums with EDAPlayground

The forums on the Verification Academy have been around for about a decade (even longer…

Mastering Today’s Emerging Functional Safety Workflows

Last week the Verification Academy announced the new Introduction to ISO 26262 “Road vehicles –…

Navigating the Road to Functional Safety

One example of increasing requirements that are contributing to growing electronic system complexity relates to…