Part 2: The 2020 Wilson Research Group Functional Verification Study

In my previous blog, I introduced the 2020 Wilson Research Group Functional Verification Study (click here). The objective of my previous…

Part 1: The 2020 Wilson Research Group Functional Verification Study

In my previous blog, I introduced the 2020 Wilson Research Group Functional Verification Study (click here). The objective of my previous…

Understanding and Minimizing Study Bias (2020 Study)

This blog is a continuation on the 2020 Wilson Research Group Functional Verification Study blog series. A big concern when…

Prologue: The 2020 Wilson Research Group Functional Verification Study

This is the first in a sequence of blogs that presents the findings from our new 2020 Wilson Research Group…

SystemVerilog Race Condition Challenge Responses

SystemVerilog Race Condition Challenge Responses

As promised, here is my response to Mentor’s SystemVerilog Race Condition Challenge Race #1 Blocking and non-blocking assignments   byte…

SystemVerilog

Time for Another Revision of the SystemVerilog IEEE 1800 Standard

Between Accellera and the IEEE, there have been seven revisions of the SystemVerilog Language Reference Manual (LRM) over the past…

SystemVerilog Race Condition Challenge

If there’s one thing I’ve learned since coming to Mentor early last year, it’s that the SystemVerilog language gives developers…

DAC 2020: A Rare Virtual Opportunity in Professional Development!

DAC 2020: A Rare Virtual Opportunity in Professional Development!

Probably one of the most important pieces of advice I ever received was given to me when I was a…

PCIe Gen5: A pathway to address Data Explosion and Emerging Technologies

PCIe Gen5: A pathway to address Data Explosion and Emerging Technologies

As the technology scales or shrinks, there are always some bottlenecks that need to be addressed sometimes it is the…