Thought Leadership

Closing the Gap in Software Skills for Verification Engineers

I’m excited to announce next month’s U2U (User-to-User) meeting, followed by a crucial technical training session that no hardware verification engineer should miss.

The U2U meeting will provide the usual platform for knowledge exchange and networking. However, what makes this event particularly special for hardware verification engineers is the following day’s training: “Introduction to Software Design Pattern Concepts in SystemVerilog and UVM.”

In today’s hardware design landscape, the lines between hardware and software are increasingly blurring. While many of us excel in hardware design, the complexity of modern verification environments demands a solid understanding of software design principles. The SystemVerilog and UVM frameworks utilize numerous software design patterns, such as:

  • Factory Pattern: Overriding deep into class hierarchy
  • Observer Pattern: Used in monitoring and scoring
  • Singleton Pattern: For managing unique resources

Understanding these patterns can significantly improve your verification environment’s maintainability and reusability. For instance, implementing the Factory pattern can reduce your SystemVerilog code base extent and complexity exponentially.

Don’t miss this opportunity to bridge the hardware-software gap and enhance your verification skills. The training will be particularly valuable for hardware engineers looking to strengthen their software design capabilities. This is just a small sampling of our language, methodology and tool training offerings.

SystemVerilog
UVM

Event Details:

  • U2U Meeting: May 20, 2025
  • Training Session: May 21, 2025
  • Location: Santa Clara Marriott, Santa Clara, CA
  • Registration Deadline: May 5, 2025

Register now through the training portal. Space is limited to ensure optimal learning experience.

Dave Rich
Principal Trainer

Dave Rich is a principal instructor at Siemens EDA and is responsible for defining and deploying advanced verification methodologies. Most recently, Dave Rich was a Verification Architect in the Product and Solutions Ecosystems team at Siemens EDA, responsible for the Verification Academy’s content and forum discussions. He has over three decades of design and verification experience in simulation and synthesis technologies. He is actively involved in SystemVerilog standardization, serving as Technical Chair of the IEEE 1800 Working Group and on the Design and Verification Conference steering committee.

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.sw.siemens.com/verificationhorizons/2025/04/17/closing-the-gap-in-software-skills-for-verification-engineers/