Simulation is Key in design verification process

The importance of simulation in the pursuit of absolute speed!

A casual conversation with an ex-insider of the high frequency trading sector reveals surprising details about simulation and their design-verification process

UVM Objections at DVCON US 2024 – and Grape Jelly

Boiling Grape Jelly Stay with me – trust me. There’s a tie in to UVM Objections and DVCON US 2024….

Accellera Day at DVCon U.S. 2024

DVCon U.S. 2024 will be a week packed with paper sessions, tutorials, panels, keynotes and more on the latest in…

Join us at DVCon for a panel on Generative AI

It’s that time of year again, and I couldn’t be more excited for the 2024 Design & Verification Conference &…

Welcome to the enhanced Verification Academy 2.0 forums!

We’ve recently enhanced the Verification Academy, moving to an all new platform. The Verification Academy is the industry’s leading resource…

Welcome to Verification Academy 2.0!

Step into the enhanced Verification Academy 2.0! After a year of meticulous development, we are thrilled to unveil its array…

IEEE Honors Siemens Employees for Dedication to Standards Development

Annually, the IEEE Standards Association (IEEE SA) recognizes outstanding participation across a variety of technical areas of standards development, leadership,…

Decoding LLM Hallucinations: Insights and Taming them for EDA Applications

What are Large Language Model’s hallucinations. LLMs will be powerful EDA productivity tool once we know what caused it and how to deal with their adverse effects.

Siemens EDA at the 60th DAC

Please mark your calendars for the highly anticipated 60th anniversary Design Automation Conference (DAC). The 60th DAC will take place…