Tessent Solutions

The Tessent silicon lifecycle solutions provide IP and applications that detect, mitigate and eliminate risks throughout the IC lifecycle, from the design-for-test phase through continuous IC monitoring. Tessent helps customers address their debug, manufacturing test, yield, functional safety, IC security, and optimization requirements for today’s most complex SoCs.

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Shift Left in DFT Design

April 10, 2025

Tessent™ RTL Pro software automates the analysis and insertion of Tessent VersaPoint™ test point technology, LBIST-OST test points, dedicated scan wrapper cells and x-bounding logic as behavioral code at the RTL level. Tessent RTL Pro builds on Tessent’s market-leading DFT tools by providing unique functionality that helps customers shorten design turnaround time and
accelerate time-to-market.

By Jayne Scheckla
3 MIN READ
Tessent UltraSight-V

Accelerating RISC-V development with Tessent UltraSight-V

February 17, 2025

Tessent UltraSight-V is a comprehensive debug and trace solution for RISC-V processors that combines embedded IP and software to enable efficient debugging and tracing while integrating with industry-standard tools to support the development of high-performance embedded software.

By Tessent Solutions
3 MIN READ

No-compromise packetized test improves DFT efforts

January 30, 2025

Design for Test (DFT) managers often must make difficult and sometimes costly trade-offs between test implementation effort and manufacturing test…

By Peter Orlando
7 MIN READ

Google and Tessent Streaming Scan Network at ISTFA 2024

November 21, 2024

Technology advancements have led to a significant increase in system-on-chip (SoC) complexity, necessitating the careful optimization of DFT techniques to…

By Peter Orlando
2 MIN READ

Maximizing SoC Performance: The Role of Embedded Software and Functional Monitors

May 7, 2024

In the rapidly evolving landscape of System on Chip (SoC) development, the demand for effective debugging and optimization is becoming…

By Tessent Solutions
2 MIN READ
Enhance safety with Tessent

Enhance safety with Tessent

February 1, 2024

Learn how to ensure safety for automotive ICs with Tessent solutions from Siemens EDA.

By Lee Harrison
5 MIN READ

The age of AI comes to IC test automation

January 18, 2024

Learn how artificial intelligence (AI) is advancing IC test and yield analysis.

By Ron Press
4 MIN READ

Video: Leveraging the RISC-V efficient trace (E-Trace) standard

January 16, 2024

Learn more about using the RISC-V efficient trace standard for non-intrusive, full-speed and system-level visibility.

By Tessent Solutions
2 MIN READ

Three ways to slash AI chip TTM with advanced DFT and silicon bring-up

December 19, 2023

Advanced EDA technology eases AI chip development.

By Lee Harrison
6 MIN READ