Latest Posts

Cornell University: Building Sparse Linear Algebra Accelerators with HLS

Sparse linear algebra (SLA) operations are essential in many applications such as data analytics, graph processing, machine learning, and scientific…

Customers Share Their Experiences Using High-Level Synthesis

High-Level Synthesis (HLS) has never been more in demand for chip design. In fact, it could be said that the…

Power: Front & Center of the Silicon Design Process

Power is one of the most critical design metrics today, but it still is an afterthought in far too many…

A hardware-centric approach to checking HLS code before synthesis

A hardware-centric approach to checking HLS code before synthesis

Excerpt from article: “A hardware-centric approach to checking HLS code before synthesis“ Finding coding problems in C++ or SystemC code…

Stanford University: Edge Machine Learning DNN Accelerator SoC Design Using Catapult HLS | Webinar

Stanford University: Edge Machine Learning DNN Accelerator SoC Design Using Catapult HLS | Webinar

This webinar describes the Edge Machine Learning Accelerator SoC design and verification of the systolic array-based DNN accelerator taped out by Stanford, the performance optimizations of the…

Welcome to: HLS Design & Verification Blog

Welcome to: HLS Design & Verification Blog

This blog will cover next generation High-Level Synthesis (HLS) design and verification methodologies and techniques. Actual users will be talking…

SemiEngineering: Why TinyML is Such a Big Deal

SemiEngineering: Why TinyML is Such a Big Deal

Excerpt from article: “Why TinyML is Such a Big Deal“ “If you just compile everything onto the controller, even at…

AI/ML Accelerator Tutorial: C-level Design & Verification Using HLS | Virtual Seminar

AI/ML Accelerator Tutorial: C-level Design & Verification Using HLS | Virtual Seminar

Catapult HLS (High-Level Synthesis) and C-level design and verification are reducing entire project development times by half or more in…

Advanced Synthesis for NanoXplore FPGAs  | Webinar

Advanced Synthesis for NanoXplore FPGAs | Webinar

Many space and mil-aero applications require the use of specialized FPGAs with built-in protection from single event upsets. NanoXplore introduces…