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AI/ML Accelerator Tutorial: C-level Design & Verification Using HLS | Virtual Seminar

Agenda Day 1 30 min – Seminar Introduction and Customer Case Studies  This session will…

Advanced Synthesis for NanoXplore FPGAs | Live Webinar

Many space and mil-aero applications require the use of specialized FPGAs with built-in protection from…

Convolutional Neural Network Quantization for Low-Power | Live Webinar

Inferencing for Convolutional Neural Network(s) (CNNs) is notoriously compute intensive. This makes them an ideal…

How MatchLib and SystemC Enables Early C-level Performance Analysis and Validation in an HLS Design Flow | Webinar

Learn how a High-Level Synthesis (HLS) design and verification flow built around Catapult HLS can…

SemiEngineering: Tradeoffs To Improve Performance, Lower Power

Excerpt from article: “Tradeoffs To Improve Performance, Lower Power“ In the past, developers could just…

image of source code running through Catapult provides the same latency for the AES core

Conversion from Vivado High-Level Synthesis (HLS) to Catapult HLS

In this blog post, we explore the key points which are required to convert an…

SemiEngineering: Designing Low Energy Chips And Systems

Excerpt from article: “Designing Low Energy Chips And Systems“ The lifecycle energy requirements of anything,…

SemiEngineering: Hidden Costs In Faster, Low-Power AI Systems

Excerpt from article: “Hidden Costs In Faster, Low-Power AI Systems” Rising design costsAnother piece of…