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SemiEngineering: Raising The Abstraction Level For Power

SemiEngineering: Raising The Abstraction Level For Power

Excerpt from article: “Raising the Abstraction Level for Power“ Architectural Power Early analysis can lead to the largest gains. “Certainly, higher…

EE Journal: Menta and Mentor Partner for High-Level Synthesis of Embedded FPGA IP

EE Journal: Menta and Mentor Partner for High-Level Synthesis of Embedded FPGA IP

Excerpt from article: “Menta and Mentor Partner for High-Level Synthesis of Embedded FPGA IP“ Siemens EDA‘s Catapult™ HLS design tools…

High-level synthesis for AI: Part One

High-level synthesis for AI: Part One

Excerpt from article: “High-level synthesis for AI: Part One“ HLS shortens design cycles by raising design abstraction above RTL, typically…

Using Less Power At The Same Node

Using Less Power At The Same Node

Excerpt from article: “Using Less Power At The Same Node“ “GPUs and artificial intelligence do require the new nodes, but it is…

SemiWiki: Mentor Showcases Digital Twin Demo

SemiWiki: Mentor Showcases Digital Twin Demo

Excerpt from article: “Mentor Showcases Digital Twin Demo“ Siemens EDA put on a very interesting tutorial at DVCon this year. Commonly…

Tech Design Forum: Catapult HLS Integrates eFPGA IP for Faster Development

Tech Design Forum: Catapult HLS Integrates eFPGA IP for Faster Development

Excerpt from article: “Catapult HLS Integrates eFPGA IP for Faster Development“ Siemens EDA is looking to extend the configurability options…