Customers Share Their Experiences Using High-Level Synthesis

High-Level Synthesis (HLS) has never been more in demand for chip design. In fact, it could be said that the…

Power: Front & Center of the Silicon Design Process

Power is one of the most critical design metrics today, but it still is an afterthought in far too many…

Stanford University: Edge Machine Learning DNN Accelerator SoC Design Using Catapult HLS | Webinar

Stanford University: Edge Machine Learning DNN Accelerator SoC Design Using Catapult HLS | Webinar

This webinar describes the Edge Machine Learning Accelerator SoC design and verification of the systolic array-based DNN accelerator taped out by Stanford, the performance optimizations of the…

AI/ML Accelerator Tutorial: C-level Design & Verification Using HLS | Virtual Seminar

AI/ML Accelerator Tutorial: C-level Design & Verification Using HLS | Virtual Seminar

Catapult HLS (High-Level Synthesis) and C-level design and verification are reducing entire project development times by half or more in…

Advanced Synthesis for NanoXplore FPGAs  | Webinar

Advanced Synthesis for NanoXplore FPGAs | Webinar

Many space and mil-aero applications require the use of specialized FPGAs with built-in protection from single event upsets. NanoXplore introduces…

Convolutional Neural Network Quantization for Low-Power | Webinar

Convolutional Neural Network Quantization for Low-Power | Webinar

Inferencing for Convolutional Neural Network(s) (CNNs) is notoriously compute intensive. This makes them an ideal candidate for hardware acceleration, which…

SemiWiki: Mentor Masterclass on ML SoC Design

SemiWiki: Mentor Masterclass on ML SoC Design

Excerpt from article: “Mentor Masterclass on ML SoC Design” I was scheduled to attend the Siemens EDA tutorial at DVCon…