Excerpt from article: “Mentor Masterclass on ML SoC Design”
I was scheduled to attend the Siemens EDA tutorial at DVCon this year. Then coronavirus hit, two big sponsors dropped out and the schedule was shortened to three days. Siemens EDA’s tutorial had to be moved to Wednesday and, as luck would have it, I already had commitments on that day. Siemens EDA kindly sent me the slides and audio from the meeting and I’m glad they did because the content proved to be much richer than I had expected.
Lauro Rizzatti and Steve Bailey provided an intro and confirmed my suspicion that this class of solutions is targeted particularly at hardware accelerators. Could be ML, video, audio, wireless algorithms, any application-specific thing you need to speed up and/or reduce power in an edge device. Maybe a surveillance product, which had been getting by with a low-res image and ML software running on a CPU, now you must move to 4K resolution with faster recognition at the same power. You need a hardware accelerator. For this tutorial they use TinyYOLO for object recognition as their demo platform.
Russ Klein came next with a nod to algorithm design (in TensorFlow using Python) then algorithm partitioning and optimization. Sounds like a big yawn, right? Some basic partitioning, changing bus widths and fixed-point sizes, tweaking here tweaking there?
Wrong – very wrong.
Read the entire article on SemiWiki originally published on March 24th, 2020.