AI/ML Accelerator Tutorial: C-level Design & Verification Using HLS | Virtual Seminar
Catapult HLS (High-Level Synthesis) and C-level design and verification are reducing entire project development times by half or more in today’s ASIC and FPGA designs. It is being used to create production-quality HW Accelerators for multiple applications such as 5G and Communication, Image and Video Processing, Automotive, and AI/ML much faster than hand-coded RTL with equivalent power, performance and area. Many new to HLS, however, have questions about how to take advantage of the productivity benefits of moving up in abstraction and still have the verification closure and confidence that they have with their current methodology.
This technical seminar will be a case study of an AI/ML accelerator design in an AMBA AXI-based subsystem. It will go step-by-step from an algorithm through C-based design and system-level performance validation, HW/SW integration, and then comprehensive verification through RTL coverage closure showing both tools and methodology.
To deliver high-quality technical content and more personal interaction, we have split the seminar to run over 2-days with approx. 3 hrs each day; the first day more heavily weighted for design and the second for verification. We have added interactive breakout sessions, live Q&A with the experts in addition to open-source examples and free On-Demand training that you can try on your own when the seminar is complete. Save your place by registering below and we look forward to seeing you live on the day.
North America Dates: June 22 & 24, 9AM-12:30PM Pacific Time
Europe Dates: June 29 & July 1, 15:00-18:30 Central European Time