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FPGA

AI/ML Accelerator Tutorial: C-level Design & Verification Using HLS | Virtual Seminar

AI/ML Accelerator Tutorial: C-level Design & Verification Using HLS | Virtual Seminar

June 17, 2021

Catapult HLS (High-Level Synthesis) and C-level design and verification are reducing entire project development times by half or more in…

By Mathilde Karsenti
4 MIN READ
Advanced Synthesis for NanoXplore FPGAs  | Webinar

Advanced Synthesis for NanoXplore FPGAs | Webinar

May 18, 2021

Many space and mil-aero applications require the use of specialized FPGAs with built-in protection from single event upsets. NanoXplore introduces…

By Mathilde Karsenti
< 1 MIN READ
image of source code running through Catapult provides the same latency for the AES core

Conversion from Vivado High-Level Synthesis (HLS) to Catapult HLS

March 5, 2021

In this blog post, we explore the key points which are required to convert an algorithm developed for Vivado HLS…

By Mathilde Karsenti
4 MIN READ
SemiEngineering: ML Opening New Doors For FPGAs

SemiEngineering: ML Opening New Doors For FPGAs

June 24, 2020

Excerpt from article: “ML Opening New Doors For FPGAs” FPGAs have long been used in the early stages of any…

By nileshthiagarajan
< 1 MIN READ
FPGA Design Tradeoffs Getting Tougher

FPGA Design Tradeoffs Getting Tougher

September 16, 2019

Excerpt from article: “FPGA Design Tradeoffs Getting Tougher” FPGAs are getting larger, more complex, and significantly harder to verify and…

By nileshthiagarajan
< 1 MIN READ