A hardware-centric approach to checking HLS code before synthesis

Excerpt from article: “A hardware-centric approach to checking HLS code before synthesis“ Finding coding problems…

Stanford University: Edge Machine Learning DNN Accelerator SoC Design Using Catapult HLS | Webinar

This webinar describes the Edge Machine Learning Accelerator SoC design and verification of the systolic array-based DNN accelerator taped…

Welcome to: HLS Design & Verification Blog

This blog will cover next generation High-Level Synthesis (HLS) design and verification methodologies and techniques….

SemiEngineering: Why TinyML is Such a Big Deal

Excerpt from article: “Why TinyML is Such a Big Deal“ “If you just compile everything…

AI/ML Accelerator Tutorial: C-level Design & Verification Using HLS | Virtual Seminar

Catapult HLS (High-Level Synthesis) and C-level design and verification are reducing entire project development times…

Convolutional Neural Network Quantization for Low-Power | Webinar

Inferencing for Convolutional Neural Network(s) (CNNs) is notoriously compute intensive. This makes them an ideal…

How MatchLib and SystemC Enables Early C-level Performance Analysis and Validation in an HLS Design Flow | Webinar

Learn how a High-Level Synthesis (HLS) design and verification flow built around Catapult HLS can…

SemiEngineering: Tradeoffs To Improve Performance, Lower Power

Excerpt from article: “Tradeoffs To Improve Performance, Lower Power“ In the past, developers could just…

image of source code running through Catapult provides the same latency for the AES core

Conversion from Vivado High-Level Synthesis (HLS) to Catapult HLS

In this blog post, we explore the key points which are required to convert an…