Cornell University: Building Sparse Linear Algebra Accelerators with HLS

Sparse linear algebra (SLA) operations are essential in many applications such as data analytics, graph processing, machine learning, and scientific…

A hardware-centric approach to checking HLS code before synthesis

A hardware-centric approach to checking HLS code before synthesis

Excerpt from article: “A hardware-centric approach to checking HLS code before synthesis“ Finding coding problems in C++ or SystemC code…

Stanford University: Edge Machine Learning DNN Accelerator SoC Design Using Catapult HLS | Webinar

Stanford University: Edge Machine Learning DNN Accelerator SoC Design Using Catapult HLS | Webinar

This webinar describes the Edge Machine Learning Accelerator SoC design and verification of the systolic array-based DNN accelerator taped out by Stanford, the performance optimizations of the…

Welcome to: HLS Design & Verification Blog

Welcome to: HLS Design & Verification Blog

This blog will cover next generation High-Level Synthesis (HLS) design and verification methodologies and techniques. Actual users will be talking…

SemiEngineering: Why TinyML is Such a Big Deal

SemiEngineering: Why TinyML is Such a Big Deal

Excerpt from article: “Why TinyML is Such a Big Deal“ “If you just compile everything onto the controller, even at…

AI/ML Accelerator Tutorial: C-level Design & Verification Using HLS | Virtual Seminar

AI/ML Accelerator Tutorial: C-level Design & Verification Using HLS | Virtual Seminar

Catapult HLS (High-Level Synthesis) and C-level design and verification are reducing entire project development times by half or more in…

Convolutional Neural Network Quantization for Low-Power | Webinar

Convolutional Neural Network Quantization for Low-Power | Webinar

Inferencing for Convolutional Neural Network(s) (CNNs) is notoriously compute intensive. This makes them an ideal candidate for hardware acceleration, which…

How MatchLib and SystemC Enables Early C-level Performance Analysis and Validation in an HLS Design Flow | Webinar

How MatchLib and SystemC Enables Early C-level Performance Analysis and Validation in an HLS Design Flow | Webinar

Learn how a High-Level Synthesis (HLS) design and verification flow built around Catapult HLS can dramatically speed up the design…

SemiEngineering: Tradeoffs To Improve Performance, Lower Power

SemiEngineering: Tradeoffs To Improve Performance, Lower Power

Excerpt from article: “Tradeoffs To Improve Performance, Lower Power“ In the past, developers could just wait for the next silicon…