A hardware-centric approach to checking HLS code before synthesis

Excerpt from article: “A hardware-centric approach to checking HLS code before synthesis

Finding coding problems in C++ or SystemC code before passing it to high-level synthesis has historically been a tricky process. It has arguably slowed HLS adoption. A recent technical paper from Siemens EDA describes how it is looking to solve this problem within its Catapult HLS tool family…

Siemens EDA’s Catapult Design Checker sits within the company’s Verification Solution for HLS. It includes a digital copy of a HLS Blue Book with guide lines of RTL-friendly coding and a series of automated processes to address the three problem types, using a hardware-centric combination of static and formal verification techniques

The flow is illustrated in Figure 1, and comprises the following steps:

Read the entire article on TechDesignForum originally published on February 26th, 2019.

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.sw.siemens.com/hlsdesign-verification/2021/09/29/a-hardware-centric-approach-to-checking-hls-code-before-synthesis/