Welcome to: HLS Design & Verification Blog

This blog will cover next generation High-Level Synthesis (HLS) design and verification methodologies and techniques. Actual users will be talking about their experiences covering a number of areas, such as:

  • Getting best Quality of Results for performance, power and area in ASIC and FPGA
  • Pure software vs synthesizable hardware in C++ and SystemC
  • Verification approaches for C++ and SystemC
  • Adopting HLS as a design methodology
  • Moving from RTL to HLS
  • Coding style tips
  • Tool tips

The blog will be very technical with code examples and explanations of how to achieve specific goals when using HLS. 

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