High-level synthesis for AI: Part One

Excerpt from article: “High-level synthesis for AI: Part One

HLS shortens design cycles by raising design abstraction above RTL, typically using SystemC, C or C++ to define the project before synthesis. This is especially useful for computer vision because of a useful alignment between the hardware and algorithmic design environments. Badru Agarwala, General Manager with Siemens EDA, explains:

“Algorithm developers prefer to write code in C++, do not want to learn register transfer languages – such as Verilog or VHDL – and they do not want to use the tools and methodologies required for the hardware implementation process,” he writes. “To address this problem, some algorithm developers write their code in C++ and then use high-level synthesis tools.”

Read the entire article on Tech Design Forum originally published on March 26th, 2019.

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.sw.siemens.com/hlsdesign-verification/2019/03/26/high-level-synthesis-for-ai-part-one/