Tech Design Forum: Catapult HLS Integrates eFPGA IP for Faster Development

By nileshthiagarajan

Excerpt from article: “Catapult HLS Integrates eFPGA IP for Faster Development

Siemens EDA is looking to extend the configurability options available from high-level synthesis (HLS) through a collaboration with Menta SAS, a provider of customizable embedded FPGA (eFPGA) IP.

The integration between Siemens EDA’s Catapult HLS tool family and Menta’s IP and accompanying Origami programmer will, the companies say, allow design teams to change eFPGA configurations at any stage of development.

Menta’s IP allows engineers to specify the size and number of embedded logic blocks (eLBs), global clocks, memory, ALUs, and interfaces as required for any application at any process node. Menta’s eFPGA fabric also supports third party IP and memory blocks.

Read the entire article on TechDesignForum originally published on March 2nd, 2019.

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This article first appeared on the Siemens Digital Industries Software blog at