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image of source code running through Catapult provides the same latency for the AES core

Conversion from Vivado High-Level Synthesis (HLS) to Catapult HLS

In this blog post, we explore the key points which are required to convert an…

SemiEngineering: Designing Low Energy Chips And Systems

Excerpt from article: “Designing Low Energy Chips And Systems“ The lifecycle energy requirements of anything,…

SemiEngineering: Hidden Costs In Faster, Low-Power AI Systems

Excerpt from article: “Hidden Costs In Faster, Low-Power AI Systems” Rising design costsAnother piece of…

SemiEngineering: Low Power Still Leads, But Energy Emerges As Future Focus

Excerpt from article: “Low Power Still Leads, But Energy Emerges As Future Focus“ Across the…

SemiEngineering: The Next Big Leap: Energy Optimization

Excerpt from article: “The Next Big Leap: Energy Optimization“ “Multiple design houses have told us…

SemiEngineering: Speeding Up AI With Vector Instructions

Excerpt from article: “Speeding Up AI With Vector Instructions” SoC designers get these benefits for…

SemiEngineering: Week In Review: Design, Low Power

Excerpt from article: “Week In Review: Design, Low Power“ Arm and Mentor are teaming up…

SemiEngineering: Custom Designs, Custom Problems

Excerpt from article: “Custom Designs, Custom Problems“ You have to put margin in your architecture….

SemiEngineering: The Evolution Of High-Level Synthesis

Excerpt from article: “The Evolution Of High-Level Synthesis“ The first panelist was Brian Bowyer, director of…