SemiEngineering: Designing Low Energy Chips And Systems
Excerpt from article: “Designing Low Energy Chips And Systems“
The lifecycle energy requirements of anything, such as a server or a mobile phone, have to be low,” noted Qazi Faheem Ahmed, principal product manager at Siemens EDA. “People typically tend to focus on power at the IP level, and they might try to reduce and optimize power by a certain percentage. Let’s say they save 20% dynamic power. How much does that actually contribute to energy efficiency at the system level? Sometimes it might not do much. You might see overall energy efficiency gains of even less than 1%. And when energy equals power/time, time becomes an important factor because it tells us something about the way the block functions.”
The best way to deal with this is at the system level. “At an SoC level, some of the blocks might not have high toggle activity, but they might be active for quite some time,” said Ahmed. “Other blocks may have bursts of information coming in, may have high toggle activity, and then just remain silent. If we look at the amount of work done, in that case, the amount of work done by a block that does not toggle so much but dominates the functionality most of the time might actually end up consuming more energy. And that might be a good place to start for optimization.”
These kinds of tradeoffs are becoming increasingly pervasive as designs become more customized and heterogeneous. Lowering the power is fairly straightforward, though. Reducing energy is more complicated, and not everything warrants the effort.
Read the entire article on SemiEngineering originally published on February 1st, 2021.