Simulation is Key in design verification process

The importance of simulation in the pursuit of absolute speed!

A casual conversation with an ex-insider of the high frequency trading sector reveals surprising details about simulation and their design-verification process


Get your free copy of the IEEE 1800-2023 SystemVerilog LRM

At last year’s Design & Verification Conference (DVCon), I presented a few changes to the upcoming revision to the SystemVerilog…

UVM Debug? Just nature doing what it does

Bent Tools and other Horrors From the Garden and UVM Debug – or Are You Still Debugging with $display?

I can’t take credit for the great flowers in the garden. It’s the tremendous rain we’ve had in California this…

Pool of parameterized handles in SystemVerilog

Groups of Class Specializations in SystemVerilog

Introduction In a previous post, I said that in SystemVerilog, once you specialize a class, you can not make a…

DVCon U.S. 2023: Expanded Accellera content

DVCon U.S. 2023 will be full of opportunities to learn about advances in design and verification technology as it returns…

To UVM Config or Not at DVCON US – Can chatGPT do it better?

It’s all about speed and productivity for Verification Engineers and Designers. And of course, the UVM is the ticket, and…

The UVM string-based Factory can print base and derived objects

The UVM Factory Revealed, Part 2

Introduction This is a follow up to last week’s high-level post on the UVM Factory. Now let’s get technical! Here…

IEEE Honors Tom Fitzpatrick

At the IEEE Standards Association’s 2022 winter awards ceremony, Tom Fitzpatrick was honored for his leadership in standards development and…

The UVM type-based Factory can print base and derived objects

UVM Factory Revealed, Part 1

Introduction When you first learn UVM, most of the concepts make sense, even if you are new to Object-Oriented Programming….