The UVM Factory Revealed, Part 2

The UVM Factory Revealed, Part 2

Introduction This is a follow up to last week’s high-level post on the UVM Factory. Now let’s get technical! Here…

IEEE Honors Tom Fitzpatrick

At the IEEE Standards Association’s 2022 winter awards ceremony, Tom Fitzpatrick was honored for his leadership in standards development and…

UVM Factory Revealed, Part 1

UVM Factory Revealed, Part 1

Introduction When you first learn UVM, most of the concepts make sense, even if you are new to Object-Oriented Programming….

A pool of specialized classes

Dig a Pool of Specialized SystemVerilog Classes

Introduction SystemVerilog classes are a great way to encapsulate both variables and the routines that operates on them. What if…

Implicit handle: this

SystemVerilog: Implicit handles

Introduction In the last blog post [SC(SECL1] Farmer Ted asked you to keep track of his animals and you wrote some…

SystemVerilog: Class Member Visibility

SystemVerilog: Class Member Visibility

Introduction Farmer Ted wants to keep track of the animals on his property and asks you to write the code….

Connect test module with interface to design with individual ports

SystemVerilog: What is a Virtual Interface?

When I learned the SystemVerilog verification features, one concept had me baffled – virtual interfaces. What are these and why…

Parking lot with an Automobile and Pickup, plus class variables

Class Variables and $cast

Introduction My previous post showed how SystemVerilog class variables can refer to base and derived objects. This post shows you…

Base and derived classes and their handles

Class Variables and Assignments in SystemVerilog

Introduction Good OOP style says you should start your project with a common base class (or several). When you want…