Thought Leadership

To UVM Config or Not at DVCON US – Can chatGPT do it better?

By Rich Edelman

It’s all about speed and productivity for Verification Engineers and Designers. And of course, the UVM is the ticket, and of course, we should configure things, so that they are flexible and parameterized and, well, configurable.

But when I try the UVM Config, I get confused and have problems.

I know – I’ll write a paper about it. But wait. There’s a new solution to writing papers. chatGPT. I’ll ask chatGPT to explain and hopefully write a paper.

On Jan 9, I asked “How can I stop the madness with UVM config”

The “answer” from chatGPT:

It is difficult to provide a specific solution without more information about the specific issues you are facing with UVM config. However, here are a few general tips that may be helpful:

  1. Make sure you have a clear understanding of the UVM config process and how it works.
  2. Make sure your testbench is properly structured and organized, with a clear separation of responsibilities between different components.
  3. Use the uvm_config_db and uvm_resource_db APIs to manage configuration settings and resources, respectively.
  4. Use the uvm_config_print and uvm_resource_print APIs to print out the current configuration settings and resources, respectively. This can be useful for debugging.
  5. Be mindful of the order in which configuration settings and resources are set, as this can affect the final result.
  6. Consider using a third-party tool or library to help manage UVM config, such as the open-source “uvmbuilder” tool.

If you are still facing issues, try to seek help from experts in the field or in forums dedicated to UVM.

Not a terrible answer, but not that great. At least it pointed out some print routines. (And it got the scary #5).

On Jan 31, I asked again – “How can I stop the madness with UVM config”


If you are facing issues with the configuration of Universal Verification Methodology (UVM), here are a few steps that may help resolve the issue:

  1. Define the testbench structure and hierarchy: A well-structured testbench makes it easier to debug and maintain your verification environment.
  2. Ensure that you have a clear understanding of the test plan and coverage goals: This will help you determine which components are needed and how they should be configured.
  3. Use the UVM configuration database: The UVM configuration database provides a centralized way to store and manage configuration parameters for your testbench components.
  4. Use a consistent naming convention: A consistent naming convention can help to avoid naming collisions and make it easier to understand the relationships between components.
  5. Use the UVM phase-based approach: The UVM phase-based approach provides a standardized way to sequence the different stages of a simulation, such as the build, connect, and run phases.
  6. Ensure that your components are properly connected: Make sure that your components are connected in the correct order and that the interconnections between components are well-defined.
  7. Debug using UVM tools: UVM provides various tools and techniques that can be used to debug your verification environment, such as the UVM scoreboards and checkers.

If these steps do not resolve your issue, consider seeking help from other sources, such as online forums, support groups, or professional services.

A worse answer?! Hard to believe.

I asked again today – Feb 14 – a worse answer even yet. It was “answered” (typed) very slowly after being locked out all morning. I guess they want me to use the pay version. No thanks.

I also asked for a one-hot counter. It failed.

I’m sure we’ll all be replaced by chatGPT someday – it apparently is creating assertion properties and other kinds of verification code now. Who knows. Maybe one day it will even be able to babysit. Right now it struggles with UVM Config.

But it gets better. A great UVM session at DVCON.

Anyhow, instead of asking chatGPT, come to DVCON in San Jose – February 27-March 2 at the Doubletree Hotel. We can talk about chatGPT and the way it will do away with Verification Engineers and maybe RTL designers.

Or better, we can talk about UVM Config and using it effectively or perhaps using something different.

Come hear “Avoiding Configuration Madness The Easy Way” and share your experiences with UVM Config. By the way, the paper has nothing to do with chatGPT and was written without help from chatGPT.

Let’s just say. There are things better than UVM Config. We can be better.

Bring your best.

At DVCON US this year, there are at least two papers about config or resources in the UVM. I’m not saying it will be an all out brawl, but there should be some interesting discussions. Bring your best, just in case it is a brawl.

Session Tuesday Feb 28 @ 9:00am : Configuring UVM

  • The Untapped Power of UVM Resources and Why Engineers Should Use the uvm_resource_db API
    Clifford Cummings, Paradigm Works, Inc.; Heath Chambers, HMC Design Verification; Mark Glasser, Cerebras
  • Avoiding Configuration Madness The Easy Way
    Rich EDELMAN, Siemens EDA
  • Tree Data Framework for Code Generation: Application of Generating UVM Testbench for Complex Designs
    Chenhui Huang, Tenstorrent Inc.; Yu Sun, Tenstorrent Inc.; Divyang Agrawal, Tenstorrent Inc.
  • Strategies to Maximize Reusability of UVM Test Scenarios in SoC Verification
    Hyeonman Park, Samsung Electronics; Namyoung Kim, Samsung Electronics; Kyoungmin Lee, Samsung Electronics

See more about the papers at DVCON this year at

Check out Siemens at DVCON at

Hope to see you at DVCON! Stop in and say hello. I’ll be at the booth and around all week.

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This article first appeared on the Siemens Digital Industries Software blog at