To UVM Config or Not at DVCON US – Can chatGPT do it better?

It’s all about speed and productivity for Verification Engineers and Designers. And of course, the UVM is the ticket, and…

ML for Verification

Unleashing the Power of Verification Data with Machine Learning

Importance of data in verification can never be underestimated, start building data assets and unlock the value with Machine Learning.

Lego Blocks

Odds and Ends

I hope that the Python for Verification Series has demonstrated that Python is a new tool in the verification team’s…

Logging in pyuvm

Logging in pyuvm This is part of the Python for Verification series of blog posts. The IEEE UVM specification (1800.2-2020)…

Cooking with a non-stick pan

Non-stick surfaces and RTL design

How to keep RTL designers from costing their co-workers dinners and bedtimes in the most efficient way possible.


Leave the House With a Clean Design

Wouldn’t it be great if there were something that would stop you from leaving the house wearing mismatched clothes – I mean without a clean design?

Explanation of “Verification” in a DO-254 program

Often times, I’m asked to define what verification activities are required for a DO-254 program. For those experienced in a…

Getting Started with Questa Memory Verification IP

By Chris Spear & Kamlesh Mulchandani  Introduction The best way to create a System on a Chip is with design…


The Semantics of SystemVerilog Syntax

Trying to grasp any programming language from scratch can be a difficult task, especially when you start by reading the…