Lego Blocks

Odds and Ends

I hope that the Python for Verification Series has demonstrated that Python is a new tool in the verification team’s…

Logging in pyuvm

Logging in pyuvm This is part of the Python for Verification series of blog posts. The IEEE UVM specification (1800.2-2020)…

Cooking with a non-stick pan

Non-stick surfaces and RTL design

How to keep RTL designers from costing their co-workers dinners and bedtimes in the most efficient way possible.

Stop

Leave the House With a Clean Design

Wouldn’t it be great if there were something that would stop you from leaving the house wearing mismatched clothes – I mean without a clean design?

Explanation of “Verification” in a DO-254 program

Often times, I’m asked to define what verification activities are required for a DO-254 program. For those experienced in a…

Getting Started with Questa Memory Verification IP

By Chris Spear & Kamlesh Mulchandani  Introduction The best way to create a System on a Chip is with design…

SystemVerilog

The Semantics of SystemVerilog Syntax

Trying to grasp any programming language from scratch can be a difficult task, especially when you start by reading the…

Proxy-driven testbench

Verification Learns a New Language

Abraham Lincoln once said, “What is conservatism? Is it not adherence to the old and tried, against the new and…

Formal Flows From a Simulation Point-of-View

At the end of Your First Step Into Formal Property Checking, I said the effort I put into understanding formal…