Bob Oden shares insights on how the Universal Verification Methodology Framework (UVMF) is revolutionizing the verification landscape. UVMF is an advanced toolset that…
Introduction Multi-die systems accelerate the scaling of system functionality, reduce risk, and facilitate the creation of new product variants. However,…
Introduction Computational storage is revolutionizing data storage by embedding computational capabilities within storage devices, significantly boosting system efficiency by reducing…
A casual conversation with an ex-insider of the high frequency trading sector reveals surprising details about simulation and their design-verification process
At last year’s Design & Verification Conference (DVCon), I presented a few changes to the upcoming revision to the SystemVerilog…
DVCon U.S. 2024 will be a week packed with paper sessions, tutorials, panels, keynotes and more on the latest in…
I can’t take credit for the great flowers in the garden. It’s the tremendous rain we’ve had in California this…
Introduction In a previous post, I said that in SystemVerilog, once you specialize a class, you can not make a…
DVCon U.S. 2023 will be full of opportunities to learn about advances in design and verification technology as it returns…
