To UVM Config or Not at DVCON US – Can chatGPT do it better?

It’s all about speed and productivity for Verification Engineers and Designers. And of course, the UVM is the ticket, and…

My Day At The Beach - Early

UVM Testbench Debug – A Day At The Beach – Right?

Some people think UVM Testbench Debug is a drag. But really, it depends. I think it’s a day at the…

Finding Data

Finding Data Another weekend of weeding. Dark Star – Ceanothus – A California Lilac in the picture. (Not a weed)….

Verilog & VHDL Debug & Weeding

A short exploration through using better debugging tools for better productivity.

Engineering Tools

Clearing the Fog of ISO 26262 Tool Qualification

Introduction Developing products to the ISO 26262 standard requires many activities across multiple disciplines. One of those activities is ensuring…

Verification Horizons | September 2021

The September Verification Horizons is Now Online!

I’m really excited to share with you a very special issue of the Verification Horizons newsletter for September, 2021. The…

Why Is My Coverage The Way It Is?

Coverage is as Coverage does Writing coverage is an art. At least it is a skill which takes imagination, practice…

Siemens EDA launches new Veloce hardware-assisted verification system

Siemens Digital Industries Software today unveiled its next-generation Veloceā„¢ hardware-assisted verification system for the rapid verification of highly sophisticated, next-generation integrated circuit (IC) designs. This is the first complete, integrated offering that combines best-in-class virtual platform, hardware emulation, and Field Programmable Gate Array (FPGA) prototyping technologies and paves the way to leverage the latest powerful hardware-assisted verification methodologies.

AMC 20-152A: A practitioners perspective

A previous post discussed the high level impact of the new AMC 20-152A guidance on DO-254 programs. That post touched…