Industrial-Grade AI in EDA
Welcome to 2025. What happened?! “Coverage” in August in Yosemite backpacking has a different meaning. In August? Snow? Lots of…
A casual conversation with an ex-insider of the high frequency trading sector reveals surprising details about simulation and their design-verification process
Boiling Grape Jelly Stay with me – trust me. There’s a tie in to UVM Objections and DVCON US 2024….
It’s all about speed and productivity for Verification Engineers and Designers. And of course, the UVM is the ticket, and…
Some people think UVM Testbench Debug is a drag. But really, it depends. I think it’s a day at the…
Finding Data Another weekend of weeding. Dark Star – Ceanothus – A California Lilac in the picture. (Not a weed)….
A short exploration through using better debugging tools for better productivity.
Introduction Developing products to the ISO 26262 standard requires many activities across multiple disciplines. One of those activities is ensuring…
