Bob Oden shares insights on how the Universal Verification Methodology Framework (UVMF) is revolutionizing the verification landscape. UVMF is an advanced toolset that…
Introduction Multi-die systems accelerate the scaling of system functionality, reduce risk, and facilitate the creation of new product variants. However,…
A casual conversation with an ex-insider of the high frequency trading sector reveals surprising details about simulation and their design-verification process
Boiling Grape Jelly Stay with me – trust me. There’s a tie in to UVM Objections and DVCON US 2024….
DVCon U.S. 2024 will be a week packed with paper sessions, tutorials, panels, keynotes and more on the latest in…
We’ve recently enhanced the Verification Academy, moving to an all new platform. The Verification Academy is the industry’s leading resource…
Step into the enhanced Verification Academy 2.0! After a year of meticulous development, we are thrilled to unveil its array…
I can’t take credit for the great flowers in the garden. It’s the tremendous rain we’ve had in California this…
Introduction In a previous post, I said that in SystemVerilog, once you specialize a class, you can not make a…
