Thought Leadership

DVCon U.S. 2023: Expanded Accellera content

By Dennis Brophy

DVCon U.S. 2023 will be full of opportunities to learn about advances in design and verification technology as it returns to an in-person event starting Monday, February 27th.  Accellera expands its plans to include three luncheon sessions.  The first one will be on Monday and the other two will be on Wednesday and Thursday.  Complete information on the DVCon U.S. 2023 program can be found here.

You can find a complete guide here if you are looking for Siemens activities at DVCon U.S. 2023. 

Siemens is an active member of Accellera and has worked to expand the content on evolving standards Accellera is developing and has released for adoption at this year’s DVCon U.S.  Expanded content includes intriguing invited talks at the Monday and Wednesday luncheon – the Chips Act and RISC-V respectively – as well as an open discussion at the Thursday luncheon on the new UVM library. 

Accellera has sponsored a half-day tutorial and several workshops which are listed below. These sessions are part of paid registration. If your time is limited, you are invited to register for the fee-free Expo pass that grants you access to evening expo social, keynote, and conference panels. Check out the registration page for more information here.

Monday – 27 February 2023

  • Portable Stimulus Working Group Tutorial: User Experiences with the Portable Stimulus Standard
    9:00 am – 12:30 pm
    The Accellera Portable Stimulus Standard is moving beyond the “bleeding edge.” As the Portable Stimulus Working Group continues to develop additional features of the language, many companies are adopting the standard in their verification flows. This technical tutorial will begin with an overview of the new features to be included in the coming update to the standard and will feature users from AMD and Intel who will share their experiences using this exciting new technology.
  • IP-XACT IEEE 1685 Working Group Workshop:  What is new in IP-XACT IEEE Std. 1685-2022?
    9:00 am – 10:30 am
    Accellera’s IP-XACT Working Group has been developing a proposal for a revision of IEEE Std. 1685™-2014. The proposal was handed over to the IEEE P1685 Working Group in late 2021 and approved by IEEE Standards Association Board in September 2022. This workshop addresses the IP-XACT user community including IP and SoC companies, EDA vendors, and research institutes to inform them about upcoming changes in IEEE Std. 1685. It also addresses examples of commercial tool support for these changes.
  • UVM-AMS Working Group Workshop: Applications of the UVM-AMS Standard
    11:00 am – 12:30 pm
    The Accellera UVM-AMS Standard will define an architecture and methodology to extend UVM testbenches from digital-only applications to DMS/real-number and AMS designs as well. This technical workshop will walk the audience through an example that will illustrate the key pieces of this approach and give a preview of how this standard will expand the ecosystem for AMS verification to allow vendors and users to create and share compatible verification components and use them in existing UVM environments.
  • Accellera Luncheon: Featuring Bob Smith Executive Director, SEMI ESD Alliance
    12:30 pm – 1:30 pm
    Accellera’s luncheon topic will feature Mr. Smith and his presentation on The CHIPS Act and Its Impact on the Design & Verification Markets.
  • IEEE 1666 Working Group Workshop: IEEE 1666-202X SystemC Sneak Peak
    3:30 pm – 5:30 pm
    The next revision of IEEE Std. 1666™ SystemC is coming! It builds on enhancements and features contributed by the SystemC community during the last decade through the Accellera SystemC Language Working Group. This workshop will present some of the features of the upcoming revision, which modernizes the language and enable new use cases. The target audience of this short workshop is system engineers, designers, and architects who are familiar with SystemC simulation and modeling concepts and would like to know which new capabilities are being introduced to enable efficient Electronic System Level (ESL) design, systems modeling, or virtual prototyping in SystemC.

Wednesday – 1 March 2023

  • Accellera Luncheon: Featuring Mark Himelstein, CTO RISC-V
    Noon – 1:30 pm
    At the Wednesday luncheon, Accellera will share a brief update on working group activities followed by an invited talk, RISC-V Everywhere presented by Mark Himelstein, CTO of RISC-V.

Thursday – 2 March 2023

  • Accellera Luncheon: UVM 1800.2-2020-2.0 Library Discussion
    12:30 pm – 1:30 pm
    UVM Working Group members will discuss the release of the 1800.2-2020-2.0 library. Presenters will focus on the implementation of the IEEE Std. 1800.2™-2020 to the library, with greatly enhanced backward compatibility using code written for UVM1.1d or UVM1.2, creating some substantial performance improvements. Questions from attendees are welcome!

Leave a Reply

This article first appeared on the Siemens Digital Industries Software blog at