Portable Stimulus 2.0 Ready for Public Review

As vice-chair of the Accellera Portable Stimulus Working Group, it is my pleasure to announce…

Accellera at Virtual DAC 2020

Functional Safety: Accellera’s Virtual Lunch Event Focus With DAC 2020 going virtual, the opportunities for…

How to Increase UVM Code Generation Productivity

I think most project teams agree that there is a lot of benefit in adopting…

How do you spell UVM? Opportunities in professional development.

A few months ago I had the honor of being invited to lecture a graduate-level…

DVCon U.S. 2020

If you have not yet registered for DVCon U.S. 2020, you can do so here….

DVCon India 2019 – Let’s Meet!

The design and verification of electronic systems is a global activity and Accellera has responded…

Mitigating Security Risks When Designing with 3rd-Party Silicon IP

Accellera DAC Panel to Discuss There is probably not one embedded system that is not…

Part 11: The 2018 Wilson Research Group Functional Verification Study

ASIC/IC Low Power Trends This blog is a continuation of a series of blogs related…

Tom Fitzpatrick Honored with Accellera Technical Excellence Award

Recognized for contributions to Verilog, SystemVerilog, UVM and Portable Stimulus Accellera has selected our own…