Join us at Accellera’s DAC Luncheon to discuss PSS

Portable Test & Stimulus Standard Takes Center Stage at Accellera’s DAC Luncheon.  The luncheon will be held on Tuesday, June…

SystemVerilog

Get your free copy of the IEEE 1800-2023 SystemVerilog LRM

At last year’s Design & Verification Conference (DVCon), I presented a few changes to the upcoming revision to the SystemVerilog…

DVCon U.S. 2023: Expanded Accellera content

DVCon U.S. 2023 will be full of opportunities to learn about advances in design and verification technology as it returns…

IEEE Honors Tom Fitzpatrick

At the IEEE Standards Association’s 2022 winter awards ceremony, Tom Fitzpatrick was honored for his leadership in standards development and…

Part 10: The 2022 Wilson Research Group Functional Verification Study

IC/ASIC Language and Library Adoption Trends This blog is a continuation of a series of blogs related to the 2022 Wilson…

Portable Stimulus 2.0 Ready for Public Review

As vice-chair of the Accellera Portable Stimulus Working Group, it is my pleasure to announce that the Portable Test and…

Accellera at Virtual DAC 2020

Functional Safety: Accellera’s Virtual Lunch Event Focus With DAC 2020 going virtual, the opportunities for social interactions have had to…

How to Increase UVM Code Generation Productivity

How to Increase UVM Code Generation Productivity

I think most project teams agree that there is a lot of benefit in adopting UVM in terms of improving…

How do you spell UVM? Opportunities in professional development.

How do you spell UVM? Opportunities in professional development.

A few months ago I had the honor of being invited to lecture a graduate-level course on functional verification. After…