Portable Stimulus 2.0 Ready for Public Review

As vice-chair of the Accellera Portable Stimulus Working Group, it is my pleasure to announce that the Portable Test and…

Accellera at Virtual DAC 2020

Functional Safety: Accellera’s Virtual Lunch Event Focus With DAC 2020 going virtual, the opportunities for social interactions have had to…

How to Increase UVM Code Generation Productivity

How to Increase UVM Code Generation Productivity

I think most project teams agree that there is a lot of benefit in adopting UVM in terms of improving…

How do you spell UVM? Opportunities in professional development.

How do you spell UVM? Opportunities in professional development.

A few months ago I had the honor of being invited to lecture a graduate-level course on functional verification. After…

DVCon U.S. 2020

DVCon U.S. 2020

If you have not yet registered for DVCon U.S. 2020, you can do so here. If you have the time,…

DVCon India 2019 – Let’s Meet!

DVCon India 2019 – Let’s Meet!

The design and verification of electronic systems is a global activity and Accellera has responded to make the DVCon’s more…

Mitigating Security Risks When Designing with 3rd-Party Silicon IP

Mitigating Security Risks When Designing with 3rd-Party Silicon IP

Accellera DAC Panel to Discuss There is probably not one embedded system that is not built without open source software,…

Part 11: The 2018 Wilson Research Group Functional Verification Study

Part 11: The 2018 Wilson Research Group Functional Verification Study

ASIC/IC Low Power Trends This blog is a continuation of a series of blogs related to the 2018 Wilson Research…

Tom Fitzpatrick Honored with Accellera Technical Excellence Award

Tom Fitzpatrick Honored with Accellera Technical Excellence Award

Recognized for contributions to Verilog, SystemVerilog, UVM and Portable Stimulus Accellera has selected our own Tom Fitzpatrick as its 2019…