I think most project teams agree that there is a lot of benefit in adopting UVM in terms of improving verification productivity and quality. Yet, let’s face it, for someone getting started with UVM it can be overwhelming and a steep learning curve. To address this, we have developed the UVM Framework (UVMF), which provides both a jump-start for learning UVM and a code generator for automating the creation of UVM verification environments. The great thing about UVMF is that it is free and available for download out on the Verification Academy. And, we have just released UVMF version 2020.1 with numerous updates and enhancements. In addition to the UVM code generators and documentation, we also offer the UVM Framework – One Bite at a Time course, also free out on the Verification Academy. This extensive consist of eighteen video training sessions covering all aspects of UVMF in small consumable portions.
So what is UVMF? The UVM Framework is a reuse methodology that verification teams can leverage. It supports component level verification reuse across projects and environment reuse from block through chip to system level simulation. The UVM Framework is an established UVM use model that is in use at many companies in multiple industries across North America and Europe.
UVMF defines an architecture and reuse methodology upon UVM, enabling teams new to UVM to be productive from the beginning while coming up the UVM learning curve. The UVM code generator (provided free in the UVMF download) automates the creation of the files, infrastructure and interconnect for interface packages, environment packages and project benches. Interface packages, environment packages, and project benches are characterized using YAML or a python API. The UVMF generator uses these characterizations to create UVM source. Once generated, developers can promptly focus on adding functionality specific to the design and interfaces used.
One of the key features of the UVM Framework is that it provides an architecture that supports both pure simulation as well as accelerated simulation using emulation. This enables the creation of a single unified environment that supports block, subsystem, chip and system level tests, and with the choice of running on a pure simulation platform (e.g. Questa) or a hardware-assisted acceleration platform using emulation (e.g. Veloce and Strato).