SystemVerilog: Class Member Visibility

SystemVerilog: Class Member Visibility

Introduction Farmer Ted wants to keep track of the animals on his property and asks you to write the code….

DVCon USA 2022 How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage

Preview of DVCon 2022 — How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage

With eight papers in two separate sessions focused exclusively on formal verification, one could assert (pun intended) that this year’s…

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Leave the House With a Clean Design

Wouldn’t it be great if there were something that would stop you from leaving the house wearing mismatched clothes – I mean without a clean design?

Verification Horizons | September 2021

The September Verification Horizons is Now Online!

I’m really excited to share with you a very special issue of the Verification Horizons newsletter for September, 2021. The…

Performance Profiling How-To (Make My Testbench Faster)

Here’s the situation… You’re DV lead. You and your team are at month 10 of a 12 month development cycle….

Simulation Performance Profiling Like a Pro

New product development is the fun part of working with Siemens. And over the past 9 months I’ve been lucky…

Part 9: The 2020 Wilson Research Group Functional Verification Study

IC/ASIC Verification Technology Adoption Trends This blog is a continuation of a series of blogs related to the 2020 Wilson…

Part 5: The 2020 Wilson Research Group Functional Verification Study

This blog is a continuation of a series of blogs related to the 2020 Wilson Research Group Functional Verification Study. …

How to Increase UVM Code Generation Productivity

How to Increase UVM Code Generation Productivity

I think most project teams agree that there is a lot of benefit in adopting UVM in terms of improving…