Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification

Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification

iTBA Introduction If you’ve been to DAC or DVCon during the past couple of years, you’ve probably at least heard…

Part 9: The 2010 Wilson Research Group Functional Verification Study

Part 9: The 2010 Wilson Research Group Functional Verification Study

Verification Techniques & Technologies Adoption Trends This blog is a continuation of a series of blogs, which present the highlights…

Part 7: The 2010 Wilson Research Group Functional Verification Study

Part 7: The 2010 Wilson Research Group Functional Verification Study

Testbench Characteristics and Simulation Strategies (Continued) This blog is a continuation of a series of blogs, which present the highlights…

Part 6: The 2010 Wilson Research Group Functional Verification Study

Part 6: The 2010 Wilson Research Group Functional Verification Study

Testbench Characteristics and Simulation Strategies This blog is a continuation of a series of blogs that present the highlights from…

Redefining Verification Performance (Part 1)

Redefining Verification Performance (Part 1)

What does the word performance mean to you? Speed? Well, obviously speed is an important characteristic. Yet, if the team…

Debugging requires a multifaceted solution

Debugging requires a multifaceted solution

PROLOGUE: Over the weekend, I was thinking about a recent visit I had with an advanced ASIC team manager who…

SystemVerilog: The finer details of $unit versus $root.

SystemVerilog: The finer details of $unit versus $root.

Another installment of “Longwinded Answers to Frequent SystemVerilog Questions: $root versus $unit” Believe me – I tried to make this…

The Language versus The Methodology

The Language versus The Methodology

I’ve been around simulation and synthesis languages for a while; back when you needed an NDA to see the Verilog…