Prologue: The 2020 Wilson Research Group Functional Verification Study

This is the first in a sequence of blogs that presents the findings from our new 2020 Wilson Research Group Functional Verification Study. Similar to my previous 2018 Wilson Research Group functional verification study blog series, I plan to separate the discussion by FPGA and IC/ASIC findings.

Study Overview

The study results presented in this blog series are a continuation of a series of industry studies on functional verification that began in 2007, and continued biennially starting in 2010 through 2020. Each of these studies was modeled after the 2002 and 2004 Collett International Research, Inc. studies and focus on the IC/ASIC market. While we began studying the FPGA market in 2012, we waited until we had sufficient multi-year data points to identify verification trends to draw any significant conclusions.

For the purpose of our study, a randomized sampling frame was constructed from multiple acquired industry lists. This enabled us to cover all regions of the world and all relevant electronics industry market segments. It is important to note that we did not include our own account team’s customer list in the sampling frame. This was done in a deliberate attempt to prevent vendor bias in the final results. While we architected the study in terms of questions and then compiled and analyzed the final results, we commissioned Wilson Research Group to execute our study. After data cleaning the results to remove inconsistent, incomplete, or random responses, the final sample size consisted of 1492 eligible participants (i.e., n=1492).

Confidence Interval

Since all survey-based studies are subject to sampling errors, we attempt to quantify this error in probabilistic terms by calculating a confidence interval. For our study, we determined the overall margin of error to be ±3% using a 95% confidence interval. In other words, this confidence interval tells us that if we were to take repeated samples from a population, 95% of the samples would fall inside our margin of error ±3%, and only 5% of the samples would fall outside.

Study Participants

This section I provide background information on the makeup of the study.

Figure 1 compares the percentage of 2016, 2018 and 2020 study participants (i.e., design projects) by targeted implementation for both IC/ASIC and FPGA projects. It is important to note that targeted implementation does not represent silicon volume in terms of the global semiconductor market since a single project could account for a significant portion of semiconductor market revenue.

Figure 1. Study Participants by Targeted Implementation

Our 2020 Wilson Research Group study is a worldwide study, and Figure 2 shows the demographics by various regions of the world. The survey results are compiled both globally and regionally for analysis. In this blog sequence we will present the global trends.

Figure 2. 2020 Study Demographics

Figure 3 shows the percentage of overall study FPGA and IC/ASIC participants by market segment. It is important to note that this figures does not represent silicon volume by market segment.

Figure 3. FPGA and IC/ASIC Study Participants by Market Segment

Figure 4 shows the percentage of overall study eligible FPGA and IC/ASIC participants by their job description. An example of eligible participant would be a self-identified design or verification engineer, or engineering manager, who is actively working within the electronics industry. Overall, design and verification engineers accounted for a majority of the study participants.

Figure 4. FPGA and IC/ASIC Study Participants by Job Title

Before I start presenting the findings from our 2020 functional verification study, I plan to discuss in my next blog general bias concerns associated with all survey-based studies—and what we did to minimize these concerns.

Quick links to the 2020 Wilson Research Group Study results

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