This is the last in a sequence of blogs that presents the findings from our new 2020 Wilson Research Group Functional Verification Study. I opened this blog series with a Prologue posting that provided an overview of this year’s study. I think it is only fitting that I end this series with an Epilogue posting that summarizes some of this year’s key findings.
We continue to receive a remarkable amount of positive feedback from this year’s study, and I think the following quote sums up nicely the general sentiment:
“I believe that the industry data that Mentor [Siemens EDA] gathers is very valuable to our organization. The data enables us to identify and gain insight into trends related to FPGA and ASIC design, including tools and methodologies. This enables us to align our organization strategies to take advantage of the solutions being developed by commercial industry. This results in cost savings and faster execution of our designs.”Executive, Mil-Aero Industry
2020 Study Summary and Key Findings
The FPGA market is going through similar complexity growing pains that the IC/ASIC market experienced in the early and mid-2000 timeframe. In particular with the emergence of SoC-class designs. Like the IC/ASIC market during that timeframe, the FPGA market today has been forced to mature its functional verification processes. This is easily measured in our study by examining the increased adoption of functional verification technology, as well as the growth in verification engineers as FPGA team members.
Perhaps the most disturbing finding from this year’s study relates to the number of FPGA projects with nontrivial bug escapes into production, as discussed in Part 2 “FPGA Verification Effectiveness.” We did find an interesting correlation between the improvement of reduced functional flaws contributing to non-trivial bug escapes, as discussed in my previous blog, and the maturing of FPGA projects’ functional verification processes.
For the IC/ASIC market, our study found continued maturing of their verification process, such as discussed in Part 9 “IC/ASIC Verification Technology Adoption Trends.” In particular, the continued increased adoption of formal technologies is encouraging.
Also for the IC/ASIC market, we were surprised by the huge increase in flaws attributed to tuning analog circuits, as discussed in Part 12 “ASIC/IC Verification Results.” One explanation to this issue is the recent increase integration of analog across the board in terms of various sized designs, and this is contributing to an increase in analog issues.
For this year’s study I have written two detailed reports. One focused on FPGA functional verification trends, and the other focused on IC/ASIC functional verification trends. You can download both of these reports by logging into the Verification Academy.
I welcome any feedback you wish to share, and I am always seeking suggestions on how to improve future versions of our studies.
Quick links to the 2020 Wilson Research Group Study results
- Prologue: The 2020 Wilson Research Group Functional Verification Study
- Understanding and Minimizing Study Bias (2020 Study)
- Part 1 – FPGA Design Trends
- Part 2 – FPGA Verification Effectiveness Trends
- Part 3 – FPGA Verification Effort Trends
- Part 4 – FPGA Verification Effort Trends (Continued)
- Part 5 – FPGA Verification Technology Adoption Trends
- Part 6 – FPGA Verification Language and Library Adoption Trends
- Part 7 – IC/ASIC Design Trends
- Part 8 – IC/ASIC Resource Trends
- Part 9 – IC/ASIC Verification Technology Adoption Trends
- Part 10 – IC/ASIC Language and Library Adoption Trends
- Part 11 – IC/ASIC Power Management Trends
- Part 12 – IC/ASIC Verification Results Trends
- Conclusion: The 2020 Wilson Research Group Functional
- Epilogue: The 2020 Wilson Research Group Functional Verification Study