The Many Flavors of Equivalence Checking: Part 6, FPGA-focused Equivalency Checking Flows

With last year’s acquisition of OneSpin, we now have a valuable addition to the solutions I described in The Many…

Cooking with a non-stick pan

Non-stick surfaces and RTL design

How to keep RTL designers from costing their co-workers dinners and bedtimes in the most efficient way possible.

Part 6: The 2020 Wilson Research Group Functional Verification Study

FPGA Language and Library Trends This blog is a continuation of a series of blogs related to the 2020 Wilson…

Part 4: The 2020 Wilson Research Group Functional Verification Study

This blog is a continuation of a series of blogs related to the 2020 Wilson Research Group Functional Verification Study…

Part 3: The 2020 Wilson Research Group Functional Verification Study

This blog is a continuation of a series of blogs related to the 2020 Wilson Research Group Functional Verification Study. …

Part 2: The 2020 Wilson Research Group Functional Verification Study

In my previous blog, I introduced the 2020 Wilson Research Group Functional Verification Study (click here). The objective of my previous…

Prologue: The 2020 Wilson Research Group Functional Verification Study

This is the first in a sequence of blogs that presents the findings from our new 2020 Wilson Research Group…

Significantly Improve Your FPGA Design Reliability by Using Custom CDC Synchronizers

Significantly Improve Your FPGA Design Reliability by Using Custom CDC Synchronizers

[Preface: we are presenting a paper on this topic at the upcoming SEE/MAPLD conference, May 21-24, 2018 in La Jolla,…

See You at DVCon U.S. 2018!

See You at DVCon U.S. 2018!

We hope to see you at DVCon U.S. 2018.  Mentor will showcase 17 papers and posters during the conference on…