Join us at Accellera’s DAC Luncheon to discuss PSS

Portable Test & Stimulus Standard Takes Center Stage at Accellera’s DAC Luncheon.  The luncheon will be held on Tuesday, June…

Navigating Reset Domain Crossings to Safety in Complex SoCs

As the complexity of system-on-chip (SoC) designs escalates, driven by the demand for more integrated functionalities and higher performance, electronic…

Simulation is Key in design verification process

The importance of simulation in the pursuit of absolute speed!

A casual conversation with an ex-insider of the high frequency trading sector reveals surprising details about simulation and their design-verification process

UVM Objections at DVCON US 2024 – and Grape Jelly

Boiling Grape Jelly Stay with me – trust me. There’s a tie in to UVM Objections and DVCON US 2024….

Accellera Day at DVCon U.S. 2024

DVCon U.S. 2024 will be a week packed with paper sessions, tutorials, panels, keynotes and more on the latest in…

IEEE Honors Siemens Employees for Dedication to Standards Development

Annually, the IEEE Standards Association (IEEE SA) recognizes outstanding participation across a variety of technical areas of standards development, leadership,…

Decoding LLM Hallucinations: Insights and Taming them for EDA Applications

What are Large Language Model’s hallucinations. LLMs will be powerful EDA productivity tool once we know what caused it and how to deal with their adverse effects.

ML for Verification

Big Data for Verification – Inspiration from Large Language Models

The importance of verification data learned from training Large Language Models. In DVCon will share an overview of ML applications in verification and . present VIQ tutorial on how data can empower verification, with demos of existing ML applications.

DVCon U.S. 2023: Expanded Accellera content

DVCon U.S. 2023 will be full of opportunities to learn about advances in design and verification technology as it returns…