Industrial-Grade AI in EDA: From Promise to Practice — A Siemens Panel at DAC 2025

Industrial-Grade AI in EDA

Generative AI: The Hype, The Hope, The Hard Truths — And the Debate at DAC

The semiconductor industry is no stranger to bold claims. But few topics today spark more debate — or more genuine…

Questa One Functional Safety

Accelerated Safety Assurance with Questa One Functional Safety Solution

Explore how the Questa One Functional Safety Solution delivers accelerated safety assurance

Questa One DFT Verification

DFT Verification: Tackling the evolving challenges

Technological advancement continues as a blistering pace, and the demand for highly reliable systems is paramount across various industries. Safety…

Accellera announces fee-free availability of IEEE Std. 1801™-2024

Accellera announced the latest revision of the IEEE Standard for Design and Verification of Low-Power Energy-Aware Electronic Systems, also known…

Update from the Standards World: Accellera Approves UVM-MS 1.0 Standard

Accellera Systems Initiative approved the Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 standard.  This milestone marks a significant advancement in…

Accellera Sessions at DVCon U.S. 2025

As one of Accellera’s Global Sponsors, Siemens EDA is happy to help shape the Accellera sessions at DVCon U.S and…

osmosis 2024

osmosis 2024 – pushing the boundaries of formal verification

Thank you for making osmosis 2024 a success! The annual osmosis 2024 event has once again proved to be a…

Ensuring robust reset integrity in complex SoC designs through advanced reset tree checks

One of the foundational steps in the reset domain crossing (RDC) verification process is determining the structure of the reset…