Pro Tip: Planning to Land Your Spacecraft on Mars? You Will Need CDC, RDC, and Formal Property Checking

If you are an engineer at one of the growing number of entities looking to land a spacecraft on Mars…

Verilog & VHDL Debug & Weeding

A short exploration through using better debugging tools for better productivity.

Engineering Tools

Clearing the Fog of ISO 26262 Tool Qualification

Developing products to the ISO 26262 standard requires many activities across multiple disciplines. One of those activities is ensuring the…

The UVM Factory

In the previous post in the Python for Verification Series, we discussed how pyuvm implemented the configuration database as a…

HDL Coding Standards for DO-254

DO-254 is the state-of-the-art standard guiding the development of airborne hardware. The document defines a hardware design lifecycle with guidance…

Debugging SoCs Can Be Complicated

There’s nothing worse than thinking you’re close to the finish line of your system-on-a-chip (SOC) design then, just as you…

Design Linting for ISO 26262

ISO 26262 remains the state of the art standard guiding the development of electronic and electronic systems destined for the…

How Can You Say That Formal Verification Is Exhaustive?

As a companion to my previous post on Learn Formal the Easy Way, allow me to explain what are often…

Stop

Leave the House With a Clean Design

Wouldn’t it be great if there were something that would stop you from leaving the house wearing mismatched clothes – I mean without a clean design?