DVCon US 2026 Keynote Verification Convergence

DVCon US Keynote: Why Verification Must Evolve in the Convergence Era

At DVCon US 2026, a keynote delivered by three speakers—Abhi Kolpekwar (Siemens EDA), Jean-Marie Brunet (Siemens EDA), and Alon Shtepel…

DVCon U.S. 2026 to be held at March 2-5, 2026

Siemens at DVCon U.S. 2026

DVCon U.S. returns to a larger venue at the Hyatt Regency Santa Clara. The expanded rooms and exhibit hall are intended to support a program heavily focused on AI in verification.

An illustration of a chip next to a computer screen representing an engineer doing formal verification

Beyond simulation: Unlocking absolute certainty in hardware design with formal verification

Explore how formal verification is revolutionizing hardware design by offering not just confidence, but absolute certainty in design’s correctness.

FutureCast 2026

FutureCast 2026: A Special Holiday Edition of BUGGED OUT

As another year closes, the semiconductor industry finds itself in a moment of transition—one where the pace of innovation is…

BUGGED OUT PODCAST

Introducing BUGGED OUT — A new bite-sized podcast for verification engineers

BUGGED OUT Podcast

Reminder: DVCon U.S. 2026 Call for Papers – Sept 7th Deadline Approaching!

The DVCon U.S. 2026 Call for Papers deadline is Sunday, September 7th at 11:59 PM. Don’t miss your chance to share your expertise…

Industrial-Grade AI in EDA: From Promise to Practice — A Siemens Panel at DAC 2025

Industrial-Grade AI in EDA

First-Silicon Success

Generative AI: The Hype, The Hope, The Hard Truths — And the Debate at DAC

The semiconductor industry is no stranger to bold claims. But few topics today spark more debate — or more genuine…

From Rule-Based Beginnings to AI-Driven Design: Tracing the Evolution of AI in EDA

As we gear up for the 62nd Design Automation Conference (DAC) in San Francisco, one of the most anticipated events…