Implicit handle: this

SystemVerilog: Implicit handles

Introduction In the last blog post [SC(SECL1] Farmer Ted asked you to keep track of his animals and you wrote some…

SystemVerilog: Class Member Visibility

SystemVerilog: Class Member Visibility

Introduction Farmer Ted wants to keep track of the animals on his property and asks you to write the code….

Connect test module with interface to design with individual ports

SystemVerilog: What is a Virtual Interface?

When I learned the SystemVerilog verification features, one concept had me baffled – virtual interfaces. What are these and why…

Finding Data

Finding Data Another weekend of weeding. Dark Star – Ceanothus – A California Lilac in the picture. (Not a weed)….

Verilog & VHDL Debug & Weeding

A short exploration through using better debugging tools for better productivity.

My Motherboard

A UVM Scoreboard: Does it really have to be that hard?

UVM Scoreboards don’t have to be hard But I’m getting ahead of myself. This week I gave up on my…

Cooking with a non-stick pan

Non-stick surfaces and RTL design

How to keep RTL designers from costing their co-workers dinners and bedtimes in the most efficient way possible.


Leave the House With a Clean Design

Wouldn’t it be great if there were something that would stop you from leaving the house wearing mismatched clothes – I mean without a clean design?

Why Is My Coverage The Way It Is?

Coverage is as Coverage does Writing coverage is an art. At least it is a skill which takes imagination, practice…