Verilog & VHDL Debug & Weeding

A short exploration through using better debugging tools for better productivity.

My Motherboard

A UVM Scoreboard: Does it really have to be that hard?

UVM Scoreboards don’t have to be hard But I’m getting ahead of myself. This week I gave up on my…

Cooking with a non-stick pan

Non-stick surfaces and RTL design

How to keep RTL designers from costing their co-workers dinners and bedtimes in the most efficient way possible.


Leave the House With a Clean Design

Wouldn’t it be great if there were something that would stop you from leaving the house wearing mismatched clothes – I mean without a clean design?

Why Is My Coverage The Way It Is?

Coverage is as Coverage does Writing coverage is an art. At least it is a skill which takes imagination, practice…

Parking lot with an Automobile and Pickup, plus class variables

Class Variables and $cast

Introduction My previous post showed how SystemVerilog class variables can refer to base and derived objects. This post shows you…

Base and derived classes and their handles

Class Variables and Assignments in SystemVerilog

Introduction Good OOP style says you should start your project with a common base class (or several). When you want…

Runtime checks with the $cast() method

Introduction Verilog was always known for its lack of type checking, treating everything as just bits strung together into vectors…

Verification Class Categories

Introduction What can you describe with Object-Oriented Programming? When I learned OOP, we had cute classes like animals, cars, and…