Introduction SystemVerilog classes are a great way to encapsulate both variables and the routines that operates on them. What if…
Some people think UVM Testbench Debug is a drag. But really, it depends. I think it’s a day at the…
Introduction In the last blog post [SC(SECL1] Farmer Ted asked you to keep track of his animals and you wrote some…
Introduction Farmer Ted wants to keep track of the animals on his property and asks you to write the code….
When I learned the SystemVerilog verification features, one concept had me baffled – virtual interfaces. What are these and why…
Finding Data Another weekend of weeding. Dark Star – Ceanothus – A California Lilac in the picture. (Not a weed)….
A short exploration through using better debugging tools for better productivity.
UVM Scoreboards don’t have to be hard But I’m getting ahead of myself. This week I gave up on my…
How to keep RTL designers from costing their co-workers dinners and bedtimes in the most efficient way possible.
