GOMACTech 2025 Preview: Improving Productivity with Parallel Simulation (Poster P.9)
Field Programmable Gate Arrays (FPGAs) continue to be a critical part of system designs, and their complexity grows as new technology allows for faster and bigger devices. Naturally, this calls for longer RTL-level simulations to allow for more realistic testing scenarios, but the time spent waiting for results often delays discovery of design bugs.
Fortunately, there is a new generation of parallel simulation technology that can address this problem by substantially reducing walk-clock run time. Specifically, at the upcoming GOMACTech conference in Pasadena, CA this March 17-20, Siemens is delivering a poster that describes the use and implementation of simulation parallelization to address the growing challenges associated with large complex FPGAs, and the ever-increasing time spent simulating for verification closure.
Here is a three-part sneak peek …
1 – Both the testbench and (FPGA-based) DUT are partitioned automatically by the tool
2 – Now, here is the best part (especially dear to users of old parallel sim technologies that failed to do the following): the tool goes on “characterize” the testbench + design, giving the user an estimate of how much an RTL simulation can be expected to improve from the partitioning and parallel sim. technology for a given test. Rephrasing, different testcases will yield different results, and not all testcases will benefit from parallel sim – so it’s quite helpful to see a test’s potential up-front.
3 – Per the above graph(s), for the verification runs that benefit from parallelization, the wall-clock run time improvements can be quite dramatic. My colleague and poster presenter Jonathan Stanley will share data from real-world case studies.
Here is the listing for the poster:
Improving Productivity with Parallel Simulation
Session P.9 – Emerging Technologies Posters
Thursday, March 20 / 10:30 a.m. – 12:00 p.m. / Exhibit Hall
(And a link to all Siemens’ activities at GOMACTech 2025)
If you don’t get to meet Jonathan in this session, please come by the Siemens booth (505) to deep-dive on this topic with him!
Joe Hupcey III
for Jonathan Stanley and the Siemens’ Questa Sim team
