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SystemVerilog: What is a Virtual Interface?

August 21, 2022

When I learned the SystemVerilog verification features, one concept had me baffled – virtual interfaces. What are these and why…

By Chris Spear
3 MIN READ
Stop

Leave the House With a Clean Design

September 14, 2021

Wouldn’t it be great if there were something that would stop you from leaving the house wearing mismatched clothes – I mean without a clean design?

By Chris Giles
7 MIN READ

Getting Started with Questa Verification IP for Protocols

February 18, 2021

The best way to create a System on a Chip is with design IP: blocks that perform common functions such…

By Chris Spear
2 MIN READ
SystemVerilog

The Semantics of SystemVerilog Syntax

February 16, 2021

Trying to grasp any programming language from scratch can be a difficult task, especially when you start by reading the…

By Dave Rich
4 MIN READ
U2U 2020 - Raytheon - CoverCheck

3 Notable Formal Verification Conference Papers of 2020

February 9, 2021

On the short list of positive things to come out of the past year are the formal verification-focused conference papers…

By Joe Hupcey III
4 MIN READ
The Many Flavors of Equivalence Checking: Part 1, Synthesis Validation with LEC and SLEC (a/k/a the Most Popular Formal Apps Ever)

The Many Flavors of Equivalence Checking: Part 1, Synthesis Validation with LEC and SLEC (a/k/a the Most Popular Formal Apps Ever)

July 11, 2019

In EDA, the word “simulation” is used everywhere: there is RTL and gate level simulation, analog simulation, RF simulation, and…

By Joe Hupcey III
5 MIN READ
New and Improved SystemVerilog 1800-2017

New and Improved SystemVerilog 1800-2017

February 23, 2018

The IEEE-SA has a policy of keeping standards active by making sure they get a cycle of updates every 10…

By Dave Rich
3 MIN READ
No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

February 12, 2018

[Preface: at the upcoming DVCon 2018 in San Jose, poster 4.12 addresses some of the issues raised below, as well…

By Joe Hupcey III
4 MIN READ
Prologue: The 2016 Wilson Research Group Functional Verification Study

Prologue: The 2016 Wilson Research Group Functional Verification Study

August 8, 2016

This is the first in a series of blogs that presents the findings from our new 2016 Wilson Research Group…

By Harry Foster
5 MIN READ