Using SystemVerilog to model RTL behavior in a pinch or anytime A couple weeks ago, sitting here in California on…
If you were not one of the 100’s of visitors to the Verification Academy booth at DAC 2015 and missed…
“Who Knew?” about verification IP (VIP), was the theme of a recent DeepChip post by John Cooley on December 18. …
Language and Library Trends This blog is a continuation of a series of blogs that present the highlights from the…
For years one of the objectives in EDA has been to make formal property checking easy to use and its…
After spending years verifying ASICs with dynamic simulation, I started working on static verification 10 years ago in a startup…
Noted EDA analyst and guru Gary Smith delivered keynote address: “ESL: Where We Are and Where We’re Going” OSCI sponsored…
I have lots of blog entries about 95% ready to publish. This entry is from an e-mail I wrote a…
I’ve been around simulation and synthesis languages for a while; back when you needed an NDA to see the Verilog…
