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Part 6: The 2020 Wilson Research Group Functional Verification Study

December 16, 2020

FPGA Language and Library Trends This blog is a continuation of a series of blogs related to the 2020 Wilson…

By Harry Foster
4 MIN READ
The Many Flavors of Equivalence Checking: Part 1, Synthesis Validation with LEC and SLEC (a/k/a the Most Popular Formal Apps Ever)

The Many Flavors of Equivalence Checking: Part 1, Synthesis Validation with LEC and SLEC (a/k/a the Most Popular Formal Apps Ever)

July 11, 2019

In EDA, the word “simulation” is used everywhere: there is RTL and gate level simulation, analog simulation, RF simulation, and…

By Joe Hupcey III
5 MIN READ
Part 10: The 2018 Wilson Research Group Functional Verification Study

Part 10: The 2018 Wilson Research Group Functional Verification Study

February 14, 2019

IC/ASIC Language and Library Adoption Trends This blog is a continuation of a series of blogs related to the 2018…

By Harry Foster
3 MIN READ
Part 6: The 2018 Wilson Research Group Functional Verification Study

Part 6: The 2018 Wilson Research Group Functional Verification Study

January 15, 2019

FPGA Language and Library Trends This blog is a continuation of a series of blogs related to the 2018 Wilson…

By Harry Foster
4 MIN READ
New and Improved SystemVerilog 1800-2017

New and Improved SystemVerilog 1800-2017

February 23, 2018

The IEEE-SA has a policy of keeping standards active by making sure they get a cycle of updates every 10…

By Dave Rich
3 MIN READ
No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

February 12, 2018

[Preface: at the upcoming DVCon 2018 in San Jose, poster 4.12 addresses some of the issues raised below, as well…

By Joe Hupcey III
4 MIN READ
Part 10: The 2016 Wilson Research Group Functional Verification Study

Part 10: The 2016 Wilson Research Group Functional Verification Study

October 31, 2016

IC/ASIC Language and Library Adoption Trends This blog is a continuation of a series of blogs related to the 2016…

By Harry Foster
3 MIN READ
Part 6: The 2016 Wilson Research Group Functional Verification Study

Part 6: The 2016 Wilson Research Group Functional Verification Study

September 21, 2016

FPGA Language and Library Trends This blog is a continuation of a series of blogs related to the 2016 Wilson…

By Harry Foster
5 MIN READ
Still waiting… It’s Friday afternoon, and I don’t have my RTL

Still waiting… It’s Friday afternoon, and I don’t have my RTL

April 20, 2016

Using SystemVerilog to model RTL behavior in a pinch or anytime A couple weeks ago, sitting here in California on…

By Rich Edelman
4 MIN READ