If you were not one of the 100’s of visitors to the Verification Academy booth at DAC 2015 and missed an opportunity to get a printed copy of the DAC 2015 issue of Verification Horizons, don’t worry. You can also download it as well.
Questa Vanguard Partners Highlighted
Eight of the eleven articles were authored or co-authored by our partners and represent a wide range of topics. There are two articles on DO-254 (Partners: eInfochips and Verisense). There is an article on Formal and ABV of MBIST MCPs (Parnter: FishTail Design Automation). There is an article on how to start formal analysis “right” (Partner: OSKI). For UVM users, reuse of MATLAB® functions and Simulink® functions is covered (Partner: Mathworks). Continuing with another article for the UVM users, intelligent testbench automation with UVM and Questa® is explored (Partner: Codasip Ltd.). For the Agile community, unit testing your way to a reliable testbench is explored (Partner: XtremeEDA & User company: NVIDIA). Lastly, a noted emulation consultant (Lauro Rizzatti) shares part 2 of his three decades of emulation evolution and a customer paper (Marvell) covers techniques to accelerate RTL simulation.
All of this is inside the 60-page mega-issue of Verification Horizons in 11 articles. Direct links to each of the articles is shared below along with the article titles and authors. The editor introduction by Tom Fitzpatrick gives even more detail and background on this issue. If you don’t already have some summer or vacation reading, get your electronic copy today!
Verifying Airborne Electronics Hardware: Automating the Capture of Assertion Verification Results for DO-254
by Vipul Patel, ASIC Engineer, eInfochips
DO-254 Testing of High Speed FPGA Interfaces
by Nir Weintroub, CEO, and Sani Jabsheh, Verisense
Formal and Assertion-Based Verification of MBIST MCPs
by Ajay Daga, CEO, FishTail Design Automation, and Benoit Nadeau-Dostie, Chief Architect, Mentor Graphics
Starting Formal Right from Formal Test Planning
by Jin Zhang, Senior Director of Marketing & GM Asia Pacific, and Vigyan Singhal, President & CEO, OSKI Technology
Reuse MATLAB® Functions and Simulink® Models in UVM Environments with Automatic SystemVerilog DPI Component Generation
by Tao Jia, HDL Verifier Development Lead, and Jack Erickson, HDL Product Marketing Manager, MathWorks
Intelligent Testbench Automation with UVM and Questa®
by Marcela Simkova and Neil Hand, VP of Marketing and Business Development Codasip Ltd.
Unit Testing Your Way to a Reliable Testbench
by Neil Johnson, Principal Consultant, XtremeEDA, and Mark Glasser, Principal Engineer, Verification Architect, NVIDIA
Hardware Emulation: Three Decades of Evolution – Part II
by Dr. Lauro Rizzatti, Verification Consultant, Rizzatti LLC
Accelerating RTL Simulation Techniques
by Lior Grinzaig, Verification Engineer, Marvell Semiconductor Ltd.
Emulation Based Approach to ISO 26262 Compliant Processors Design
by David Kaushinsky, Application Engineer, Mentor Graphics
Resolving the Limitations of a Traditional VIP for PHY Verification
by Amit Tanwar and Manoj Manu, Questa VIP Engineering, Mentor Graphics